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Arria V dual fpga pcie endpt - AN532 & AN431, has anyone ported either to dev board?

Altera_Forum
Honored Contributor II
1,011 Views

Hi, 

 

I'm trying to port the AN431 pcie endpoint design example to the dual Arria V development board. Has anyone done this already? If yes, would you be able to share the input signals that the generated Qsys module would require? I've got somewhat of an idea, but there are many other input signals that I'm not familiar with.  

 

Also, I noticed that the ddr3 design example seems to be the only one found for this board. I'd like to be able to plug the dev board into my pc's PCIe slot and run the endpoint on it. Can you confirm the IO standard I would need for the pin assignment? Are the pci lanes supposed to be 1.5V-PCML or 1.4V-PCML?  

 

Thanks, 

peter
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Altera_Forum
Honored Contributor II
116 Views

I see the 1.4V PCML in the demo qsf. Now going to map the pcie pins to the top-level. I've also posted my latest top level instantiating the endpoint. Still not totally sure about how to drive the hip_pipe_ and alt_xcvr_reconfig_0_reconfig_mgmt signals.

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