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Altera_Forum
Honored Contributor I
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Arria V strange behavior when NIOS II runs.

I have an Endpoint with IMEM for NIOS and IMEM for MAILBOX and the host system ( RC ) can read and write the MAILBOX fine .. when viewing the MAILBOX memory from the host system with static data , it is fine but when I run NIOS code to display the MAILBOX memory , NIOS displays it correctly ...  

The problem is that after running NIOS, the host system sees unstable data in the MAILBOX memory . not random data but where the pattern 0, 1, 2, 3 is displayed ... it sometimes is displayed like via a pipeline ie x, 1, 2, 3, 4 ....  

 

I have tried setting single DW completer in the PCIe IP but that didn't help. I'm going to switch to the Cyclone card to see if I get the same result. 

 

 

Last time I saw similar things, setting single DW completer on for the Cyclone card PCIe IP fixed the issue but I never got to root cause.  

 

I suspect that once the NIOS II is out of reset and started, it does something to the AVALON MM fabric that effects the PCIe IP access to the IMEM that is shared. 

I have dried dual-porting the MAILBOX memory previously and that didn't fix the issue on Cyclone.  

 

Worst case I will have to go to simulation of PCIe, IMEM, NIOS II and the MAILBOX memory but that is quite a bit of work to see if I can reproduce the behavior in simulation. 

 

Thanks, Bob. 

 

Any ideas appreciated.
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Altera_Forum
Honored Contributor I
32 Views

 

--- Quote Start ---  

I have an Endpoint with IMEM for NIOS and IMEM for MAILBOX and the host system ( RC ) can read and write the MAILBOX fine .. when viewing the MAILBOX memory from the host system with static data , it is fine but when I run NIOS code to display the MAILBOX memory , NIOS displays it correctly ...  

The problem is that after running NIOS, the host system sees unstable data in the MAILBOX memory . not random data but where the pattern 0, 1, 2, 3 is displayed ... it sometimes is displayed like via a pipeline ie x, 1, 2, 3, 4 ....  

 

I have tried setting single DW completer in the PCIe IP but that didn't help. I'm going to switch to the Cyclone card to see if I get the same result. 

 

 

Last time I saw similar things, setting single DW completer on for the Cyclone card PCIe IP fixed the issue but I never got to root cause.  

 

I suspect that once the NIOS II is out of reset and started, it does something to the AVALON MM fabric that effects the PCIe IP access to the IMEM that is shared. 

I have dried dual-porting the MAILBOX memory previously and that didn't fix the issue on Cyclone.  

 

Worst case I will have to go to simulation of PCIe, IMEM, NIOS II and the MAILBOX memory but that is quite a bit of work to see if I can reproduce the behavior in simulation. 

 

Thanks, Bob. 

 

Any ideas appreciated. 

--- Quote End ---  

 

 

The "same" design with Cyclone Transceiver Kit works fine
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