Does anyone have experience with updating the EPCQL1024 flash via PCIe? (i.e. Host <=> PCIe <=> FPGA <=> EPCQL1024)
I am looking for help on what are the steps/process that the PCIe driver needs to follow to successfully modify the Flash.
Here is how my FPGA/Hardware looks like:
PCIe Gen2x4 AVMM <=> AVMM Clock Crossing Module <=> ASMI IP <=> EPCQL1024
The clock crossing bridge manages the Transition from 125MHz (i.e. PCIe) domain to the 25MHz (i.e. ASMI) domain. I have configured the FIFO as depth of 16.
From the Host (i.e. processor) I am able to read the registers and memory successfully.
When attempting to write the new file, it does not work -- i.e. either the update fails or the PCIe hangs.
Any tips/help/insights will be super helpful. Thank You in advance!
There are few component in your design like PCIe, asmi and flash controller. I think first we should narrow down the issue to see where the problem come from.
For PCIe, you can try the lspci command from the host to see is the PCIe is detected. Or from the FPGA, you can signaltap the signals like below and understand the problem.
ltssm, currentspeed, serdes_pll_locked, pin_perst, npor, dlup, lane_act
Hello, Thank You for the response. Let me clarify further:
If you have a set of steps/instructions that I can follow, please let me know. Thanks!
May I know how do you connect your PCIe to the ASMI IP? Have you tried using Serial Flash Controller IP? Could you provide the detail step on how you performed the write operation?
Hi @JShel4 ,
Had you overcomed your problem of "PCIe Gen2x4 AVMM <=> AVMM Clock Crossing Module <=> ASMI IP <=> EPCQL1024 " writing operation ? I have a project which needs a similar function, and I'm also wanto leatn HOW TO Implement it.
Any advices are appreciated .
Thanks & Best Regards