Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
48 Views

Assignment Inconsistent with Chip planner

Hello Everyone,

 

I came across an issue with register assignment using TCL scripts in .qsf file of the project. The software I used was Quartus 18.1 standard edition.

 

One strange issue occurs with the assignment which is mismatch of assigned logic in TCL with the implemented logic in chip planner.

 

For one example, I want to assign a clocked flip flop called detector to the place "FF_X10_Y19_N17" and so my tcl is:

set_location_assignment FF_X10_Y19_N17 -to "delay_detection:UUT|detector".

 

However when I check this place in resource editor in chip planner, I found a combinational circuit assigned to it named "delay_out". This circuit's output is connected to the FF detector I want to assign.

 

To show this issue graphically, I have attached a file for your reference.

 

Could anyone please kindly explain what has happened? Is it because the display in resource editor is wrong or something goes wrong with my assignment, or the software has issues.

 

Thank you very much!

Mingqiang

0 Kudos
3 Replies
Highlighted
28 Views

Re: Assignment Inconsistent with Chip planner

Hi,

Can you provide the test case and steps to reproduce the error?

 

Thanks.

Best regards,

KhaiY

0 Kudos
Highlighted
28 Views

Re: Assignment Inconsistent with Chip planner

Hi KhaiY,

Thank you for your concern!

 

It seems that we meet agian, and you helped me with the topic "Ignored Buffers in Delay Line Design" before.

 

This is a continued version from that one and here I have attached the updated archieved project for your reference again.

 

After running "fitter" of the compile stage, a combinational circuit "delay_out" is found in resource editor at the location FF_X10_Y19_N17, whereas we expect to see a flip flop.

 

This is the most confusing part and I do not know why this happens. All location assignments are in the txt file of my previous attachment "Assignment_inconsistency".

 

Could you please help me with this?

 

Thank you!

Mingqiang

 

 

0 Kudos
Highlighted
22 Views

Re: Assignment Inconsistent with Chip planner

Hi Mingqiang,

If you refer to the Technology Map Viewer, the input of detector is connected to an output of a com binational logic named delay_out.

Capture.PNG

When you locate in Resource Property Editor, you will see the connectivity between the delay_out and detector. The location for the detector is corect, which is FF_X10_Y19_N17.

Capture2.PNG

 

Please let me know if you have any questions.

Thanks.

Best regards,

KhaiY

0 Kudos