Audio CODEC AIC23 vhdl/verilog

[Altera_Forum]

Hello, We have a Altera EP2S60 development board (http://www.altera.com/products/devkits/altera/kit-dsp-2s60.html) , which has a Stratix II FPGA and AIC23 Audio CODEC. Altera does not have any controller or IP for controlling this audio codec. I am just wondering does any of you guys have any Verilog/VHDL example codes to control this audio codec. If you do not have then could you please direct me somewhere from where I will be able to get it. Your help would be highly appreciated. Thanks.

[Altera_Forum]

You require SPI/I2C controller to control CODEC and need I2S controller for Audio Interface. You should be able to find SPI controller in SOPC builder. For free Verilog/VHDL code of I2C controller and I2S Controller, you can visit www.opencores.org. And if you planning to FPGA proven controller there are so many IP vendors providing I2S and I2C controller IP core. I guess if you want to buy IPs, you should visit www.slscorp.com for I2C and I2S controller. 

 All the best, Ketan

[Altera_Forum]

Basically both interfaces are simply shift registers with a bit counter, that controls chip select respectively data latching, additionally a clock divider Just a few lines of HDL code.

[Altera_Forum]

Thanks for replying. Unfortunately, the I2S is the easy part. It's setting up the 

data frames, which is specific to the AIC23, is most of the work. Does anybody have any example or any IP regarding that ? Thanks for ur help in advance.

[Altera_Forum]

Hi, The attached is a Quartus II project for 2S60 DSP kit. The design includes Verilog codes for AIC23 audio CODEC, which digitize Line-in analog and play back to Line-out. 

 The sample is fully controlled by a HDL state machine, but normally I use a Nios II controlled version and it’s much more flexible. If you love Nios II I will attach it.

[Altera_Forum]

Hello EOFZ, 

 Thanks a lot for your helpful reply. I really appreciate that. I will try to check this program soon. If I have any question I will ask you then. Could you please attach the NIOS II controlled version also ?  Thanks again.

[Altera_Forum]

Hi Blue Sky, 

 My design might not be readable, welcome your comments and questions.  Perhaps, I can upload Nios II version by next week. This version controls AIC registers in I2C mode using opencores IP.

[Altera_Forum]

Hi Blue Sky, 

Please update the aic23_avalon_mm_ctrl.v file as following:  Replace line# 56:  if (~wr_n)  with  if (~wr_n & ~waitrequest). This protect av_data when wr_n assertion comes too early.  BTW. If you have some about Ethernet, please post on the forum. I have no experience of it and I can not reach you through e-mail…

[Altera_Forum]

I am trying to implement a 32-tap band pass filter using the audio codec. i tried to connect the adc_data to input of the filter and dac_data to output of the filter in top.v. But it is not working. 

Please help me with the protocols between the two modules. Thanks

[Altera_Forum]

Hi pluhadia, 

If you post your sample code, you may get helpful advice.

[Altera_Forum]

Hi EOZF, this is the behavioral sample code. It is working in the software simulation but it is not working in real time application. 

 coeffs[32] = {,,,}; //32 tap low pass filter coeffs precalculated x[32];  thread { input = read input port; x[0] = input; output = 0; for (i=0; i<32; i++) {  output = output + (x*coeff); //convoluting input with filter coeffs }  for (i=32; i>0; i--) {  x[i]=x[i-1]; //need to store 33 samples of input  } write output to output port; } //end of thread   In top.v: always @(clk_in_40M) begin  if(adc_dac_enable) begin  module_input_port <= adc_data_L;  end end  always @(clk_in_40M) begin  if(adc_dac_enable) begin   dac_data_L <= signal_from_module_output_port;  dac_data_R <= signal_from_module_output_port; end end

[Altera_Forum]

Hi pluhadia, 

I have no idea how you synthesize the behavioral code into hardware, but…. If you set   coeffs[32] = { 1, 0,0,…..0}; // all zero except for the first element  How does it work?

[Altera_Forum]

Hi pluhadia, 

I’ve missed “posedge” in registering dac_data in top.v. Latches are inferrd instead of registers. This may cause timing problem in your design. Please add “posedge” at always line:  // Play back input data wire adc_dac_enable; always @( posedge clk_in_40M) begin  if (adc_dac_enable) begin  dac_data_L <= adc_data_L;  dac_data_R <= adc_data_R;  end end

[Altera_Forum]

Hi EOFZ, 

I am confused about what to connect to the input and output ports of the filter module. Should  filter_input_port <= adc_data_L;and dac_data_L <= signal from filter output port;  dac_data_R <= signal from filter output port; OR module_input_port <= adc_data_reg;and dac_data_L <= [31:16]signal from filter output port; dac_data_R <= [15:0] signal from filter ouput port;  I appreciate your help.

[Altera_Forum]

Hi pluhadia, 

Unfortunately, I don’t understand your behavioral design. What do these mean ?  filter_input_port  signal from filter output port  adc_data_reg  If you use VHDL or VerilogHDL, it is easy for me. Here is a sample 4-tap averaging FIR for left channel, which can be used in top.v.  reg signed [15:0] tap1, tap2, tap3, tap4; reg signed [17:0] filter_out; always @(posedge clk_in_40M) begin  if (adc_dac_enable) begin  tap1 <= adc_data_L;  tap2 <= tap1;  tap3 <= tap2;  tap4 <= tap3;  filter_out <= tap1 + tap2 + tap3 + tap4 ;   dac_data_L <= filter_out[17:2];  end end

[Altera_Forum]

what happens to R channel in the above 4-tap averaging filter design. To hear the filtered output in the real time implementation on hardware, 

does R channel remain unconnected  Or is it filtered the same way as L channel  Or If I do dac_data_R <= adc_data_R; (pass it as such)

[Altera_Forum]

The sample code does nothing to R channel output(dac_dagt_R) to simplify and shorten the code.  

To sound R channel, please add another filter for dac_data_R, or connect adc output directly, etc., … what ever you want to hear.

[Altera_Forum]

I can hear the filtered output but it is accompanied with a lot of noise. Is the noise caused by: mistiming of signals or filter operation

[Altera_Forum]

Hi pluhadia, 

 I don't hear any nosie. The problem may be in your hardware or design.   1. Which devkit do you use?  2. Can you hear clear sound with the original top.v?

[Altera_Forum]

I figured out the noise problem, I didn't use "signed" reg for the following, using unsigned reg was causing the noise, though I don't understand why it should happen.  

reg signed [15:0] tap1, tap2, tap3, tap4; reg signed [17:0] filter_out;  

[Altera_Forum]

Without signed keyword, you must extend sign bit by yourself for signed adder. Please refer to VelilogHDL text book for more detail. 

reg [15:0] tap1, tap2, tap3, tap4; reg [17:0] filter_out; always @(posedge clk_in_40M) begin  if (adc_dac_enable) begin  tap1 <= adc_data_L;  tap2 <= tap1;  tap3 <= tap2;  tap4 <= tap3;  filter_out <= { {2{tap1[15]}}, tap1} + { {2{tap2[15]}}, tap2} +  { {2{tap3[15]}}, tap3} + { {2{tap4[15]}}, tap4} ;   dac_data_L <= filter_out[17:2];  end end