FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
5969 Discussions

Avalon MM BFM - test program



I referred to the Avalon Verification IP suite user guide along with the example design given the document.
In the zip file, for 1x1 master - slave design, there is testbench (tb.sv) which instantiates qsys top dut and an example test program(test_program.sv).

I want to use the BFMs with my custom IP containing 1 master and 1 slave in the top, I am getting few doubts with respect to the test program and the APIs mentioned in the user guide.
I tried to simulate my dut with the test program provided in the example design with little modifications, and below are the issues/ doubts I am facing.

I am expecting the master bfm to send me some particular write data ( avs_writedata ) at address 0 (avs_address ) whenever the <avs_write> is high.
But using the test program for write transction, I am not getting any master bfm signals.
The test bench runs for few cycles displaying info messages, then stops simulation with this message - " FAILURE : verbosity_pkg.abort_simulation: abort the simulation due to fatal error incident ".

1) What is the purpose of test program? I see the APIs being used in test program.
Can I use the test program directly in my test bench to start write transaction?

2) If no, please tell me how and where to use the APIs ( in test bench or test program)?
Should I be using the test program in test bench as given in example design?

3) Do I need to modify the test program according to my custom Ip transaction requirements?

Please suggest the changes/modifications i should do to the existing test program.sv or testbench( attached below), since I am new to system verilog and all this confusing me.

Thanks in Advance.




0 Kudos
2 Replies


Here is a guide that you can check, here you can take a look at how to simulate custom components.

It is a complete flow chart that you will see at page 22 on the link [1]

Also, you can check this tutorial of how to simulate a Nios ll processor design, it is very helpful. [2]

[1] https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/tt/tt_qsys_intro.pdf


Let me know if any of this info works for you.

Best regards.

0 Kudos

Hello Ssrb,

Did these info works for you?

Best regards.

0 Kudos