Avalon MM bridge with different time clk

[CAlex]

Hi

I'm using cycloneVsoc.

I now want to get data from hps to fpga.

I have two clk ,50MHZ one, which control the FPGA,and a 200 MHZ one control the HPS lwh2f axi bridge.

If I use the avalon mm pipeline bridge ip to connect these two ports, which is correct the bridge IP's clk?

Can bridge IP use the slow clk for the FPGA ? If that is legel, do I need to ,for example, extend the signal from the fast clk region to slow one? Or the bridge IP can handle itself automatically?

Thank you 

Reguards

Alex

[JingyangTeh_Altera]

Hi Alex

Good day!

This will be done automatically by the platform designer.

The platform designer will be able to connect both agent and host with different clock together.

Regards

Jingyang, Teh

[JingyangTeh_Altera]

Hi

Any more follow up question for this thread?

Regards

Jingyang, Teh

[JingyangTeh_Altera]

Hi

Since a solution have been provided and no feedback was received, I shall set this thread to close pending. If you still need further assistance, you are welcome to reopen this thread within 20days or open a new thread, some one will be right with you. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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Regards

Jingyang, Teh