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Altera_Forum
Honored Contributor I
1,173 Views

BCLK on WM8731

Hi , 

 

I am trying to grab incoming ADC data and also sending out data to DAC on WM8731. Now the datasheet says the max clk for bclk is 20Mhz , and the toggle btw L and R channel should be 1/fs , if i am configuring the Codec for 384 fs , what should be my ADCLRC signal toggling at and what should be BCLK frequency ??? 

 

Thanks in advance
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4 Replies
Altera_Forum
Honored Contributor I
87 Views

I just wanted to add that i have set the sampling rate for the ADC and DAC to be 48Khz , actually i am following the neuron_audio_codec example . But what i dont understand that the datasheet mentions that the max BCLK can go up to 20MHz but it does not mention the min range , what if i want to run BCLK at 40khz will it still spit out data at 40Khz serially? :( 

 

well technically it is not possible since WM8731 dosent have a any memory storage or buffering resurces ,:confused: 

 

And yes the question of ADCLRC signal time period is dependent on what BCLK is since ADCLRC signal has to be high for 16 clock pulses of BCLK .
Altera_Forum
Honored Contributor I
87 Views

Nobody wants to shed some light on this issue ????????

Altera_Forum
Honored Contributor I
87 Views

 

--- Quote Start ---  

I just wanted to add that i have set the sampling rate for the ADC and DAC to be 48Khz , actually i am following the neuron_audio_codec example . But what i dont understand that the datasheet mentions that the max BCLK can go up to 20MHz but it does not mention the min range , what if i want to run BCLK at 40khz will it still spit out data at 40Khz serially? :( 

 

well technically it is not possible since WM8731 dosent have a any memory storage or buffering resurces ,:confused: 

 

And yes the question of ADCLRC signal time period is dependent on what BCLK is since ADCLRC signal has to be high for 16 clock pulses of BCLK . 

--- Quote End ---  

 

 

Hi, 

 

if you check figure 26 of the WM8731 datasheet, you'll see that what needs to be fixed is only ADCLRC signal (should be 1/fs). The bit clock (BCLK) though can run faster and you obviously should read only during the first 16 cycles of BCLK after each transition of ADCLRC. Or at least that's how I understand this, since I haven't tested anything yet. 

 

cheers 

g
Altera_Forum
Honored Contributor I
87 Views

it seems I was wrong above. I copy from the datasheet: 

 

"in slave mode, DACLRC and ADCLRC inputs are not required to have a 50:50 mark-spaace ratio. BCLK input need not be continuous. It is however required that there are sufficient BCLK cycles for each DACLRC/ADCLRC transition to clock the chosen data word length..." 

 

So, ADCLRC doesn't need to be fixed... 

 

cheers 

g
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