BURST ACCESS with UNIPHY DDR-FPGA and DDR-HPS memory controller in CYCLONE V, using QUARTUS Prime 18

[GuilleJake]

WRITE BURSTS

Since the beginbursttransfer signal no longer exists, if you want to concatenate successive write bursts:

Q: is it necessary to enter a dead cycle with write=0 at the end of each burst so that the driver reads the new writeaddress and the burstcount value at the start of the next burst?

Q: How can this dead cycle be avoided?

READ BURSTS:

In this case a single master wants to read a contiguous block of memory through successive read bursts, for example with burstcount=8.

For a single read burst we have interpreted that:

Since the beginbursttransfer signal no longer exists, a read burst is commanded to the controller when in one cycle simultaneously the signal read=1 and waitrequest=0, and it is in that cycle when the burstcount value is copied (beginbursttransfer is no longer needed nor available on QSYS). And that after that cycle the read signal MUST go to 0. And the data to be read is available only when readvalid=1 indicates it, regardless of the value of the read and waitrequest signals.

Q: Is it like that?

For contiguous read bursts we have interpreted that:

Once a master has ordered a read burst cycle, if it (or another master) wishes to order another read-burst cycle that sequence can be performed without waiting for the end of the current burst reading, and the new ordered cycle is accepted and stays on hold within the controller. The pending commands are served in the sequence it were ordered.

Q: Is this the case?

Q: And if so, how many read-burst commands on hold can the UNIPHY controller store?

[AdzimZM_Intel]

Hi GuilleJack,

I'm Adzim. Thanks for using Intel Community.

Yes you are right about the beginbursttransfer signal.

The beginbursttransfer signal exists to support the legacy memory controllers as stated in the Avalon Interface Specification at page 17.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf

There are a lot of information regarding to your question that contain inside the Avalon document.

You should refer to the link above in chapter 3.5 about the read and write transfer processes.

For the maximum burstcount, you should count it with the formula 2^(N-1) where N is width size.

The width should be 1 - 11.

Regards,

Adzim

[AdzimZM_Intel]

Hi sir,

I hope your doing well.

Do you have any further question on this topic?

I can't let this ticket opened without any activity.

I hope you understand that.

Thanks,

Adzim

[GuilleJake]

Dear Adzim

If you look carefully at my original post I've made 5 questions, all related to management of contiguous burts, and about the need (or not) of inserting dead cycles in between (in my application I have to transfer blocks of 200 Mbytes at maximum speed to DDR-FPGA external DDR3 RAM). Your answer didn't give any response, you`ve sent me to read the databooks (thing I obviously made BEFORE asking here) and a formula about burstcount that is not related to my questions. Obviously the ticket stays open, I'm yet waiting for an effective answer. I'm not an FPGA beginner, I've been ALTERA FAE for ARROW Latin America for 15 years, and I've been in charge of ALTERA University Program for Spanish speaking countries for near two decades (Ralene Marcocchia's gold era) teaching about FPGA Design everywhere, from Mexico and Spain to Argentina.

[GuilleJake]

Dear Adzim

Your phrase "The Figure 15 in Avalon Interface Specification document has shown the contiguous read burst operation."  is a perfect way to explain my question. In this figure two master nest two burst read requests ... but using beginbursttransfer to insert each request. Since beginbursttransfer is not available any more as an Avalon signal ....

How should these two master make the same operation WITHOUT having beginbursttransfer available?

How does the memory controller know that the masters want to insert a bursttransfer request?

Is the task of beginbursttransfer  now replaced by the activation of "read" signal alone (with burstcount /= 1 to signal that it is a burst read request)?

Thanks

Guillermo

[AdzimZM_Intel · Accepted solution]

Hi GuilleJake,

The controller can identify the burst operation from user's command.

When user assert the address, burstcount, read or write and data, the controller knows that the user want to do the burst operation starting at the address with the burstcount value.

So when there is a burst signal such as burstcount, the controller will know that this is a burst operation.

Then the controller will act accordingly to do the burst operation.

They do not need the beginbursttransfer signal to start the operation because the controller is smart enough to identify the operation.

Thanks,

Adzim

[AdzimZM_Intel]

Hi GuilleJack,

The memory controller can perform the burst operation without the beginbursttransfer signal.

When you assign a command to perform the burst operation, the controller knows when to start the operation.

For your read burst questions, you are right for both read burst operations.

The Figure 15 in Avalon Interface Specification document has shown the contiguous read burst operation.

The amount of the commands that can be held is set in the Starvation limit for each command in the EMIF IP.

You can find it in the Controller Settings under the Efficiency section.

The limit is at 63 commands.

Thanks,

Adzim

[AdzimZM_Intel]

Hi Guillermo,

Are you satisfy with my last comment?

Do you have further question on this case?

Regards,

Adzim