Basic Question aout I/O Pins on MAXII

[Altera_Forum]

Hi guys! 

I'm relatively new to FPGA's and CPLD's. I have successfully used and programmed a Cyclone V dev board in university, so i understand the basic principles of Quartus 2.  Now I wanted to continue experimenting with CPLDs, so I have set up an USB-Blaster and a simple MAX II Test Board where all pins are accessible via pin headers. Quartus (under Linux) successfully writes and verifys the MAXII (EPM240T100C5) Chip, but the output pins don't behave as I expect.  As a test, I have connected a few outputs to GND and VCC in Quartus. When I connect an LED (through a resistor), it's always on. I was expecting it to be off, when I connect it to the outputs that are supposed to be on GND. The screenshots show my settings.  I hope this problem can be solved pretty easily, so I can finally start experimenting with some logic :)  Best, Adrian.

[Altera_Forum]

Okay, it works now. It must have been something with the workflow in Quartus. Maybe you could explain a few more things to me: 

 I've done these steps in this order:  - Create new project - Create .bdf file - "Start Analysis & Elaboration" - Assign I/Os in the Pin Planner - "Create Top-Level Design File" (In the Pin Planner)  - Compile   - Is it necessary to create the "Top-Level Design File" in the Pin-Planner? - If I want to make changes in the .bdf file and program them into the hardware, do I run through the exact same steps again?  I've read the quick tutorial by Altera, but it only tells you what steps to take, without further explanation.  Best, Adrian.

[Altera_Forum]

Hi Adrian, 

By default the bdf file that you have created will be auto-assigned as top level design file. You would not need to create the top level again at the pin planner.

[Altera_Forum]

"If I want to make changes in the .bdf file and program them into the hardware, do I run through the exact same steps again?" 

 Regarding this Q, if any changes done to the bdf file which does not involve pin location change, you can just edit bdf -> save -> rerun compilation. You would not need to create project, assign IO or create top level again.

[Altera_Forum]

--- Quote Start ---  You would not need to create project, assign IO or create top level again.  --- Quote End ---    Yes, I would not have created a new project ;) but thanks for making clear that I only need to change the .bdf file!  Can you tell me a resource where I can read and understand exactly what the different files and steps in the process do? For example the "Start Analysis & Elaboration"..  Best, Adrian

[Altera_Forum]

--- Quote Start ---  Yes, I would not have created a new project ;) but thanks for making clear that I only need to change the .bdf file!  Can you tell me a resource where I can read and understand exactly what the different files and steps in the process do? For example the "Start Analysis & Elaboration"..  Best, Adrian  --- Quote End ---    Adrian,  There are Design Guidelines documents that are a good read. An example is this one: https://altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/max-10/m10_guidelines.pdf  Each part has its own, but it helps get an idea of the "recommended" flow for design and the issues that can arise. For the general process and what each step does, I'd work through a few of the examples that are available online or provided with Quartus. The Quartus II manual has everything, but it's also not the best reading. Hope this helps.