BeMicro CV - Qsys starter project?

[Altera_Forum]

I give up: after much googling, I'm unable to find any starter Qsys-based projects for the BeMicro CV. 

 Is anybody aware of anything I might be overlooking?  I was hoping for NIOS+DDR3 Hard IP+PIO's for the switches/LED's, but right now it looks like I have to start from scratch with the .qsf assignments from the "ddr3_example".

[Altera_Forum]

Did you ever get one built? 

 I have one from an Arrow FAE.

[Altera_Forum]

--- Quote Start ---   I have one from an Arrow FAE.  --- Quote End ---    I'm interested in seeing that if you can share. If you do not want to post it, email me directly.  Here's my 'basic' (blinky LEDs) example for the kit. I haven't got around to creating the DDR interface for it. I was going to use the examples provided with the kit to figure out the controller settings. It wouldn't hurt to have another example.  Here's the readme.txt in the zip   Bemicro-CV 'basic' design ------------------------- 4/20/2014 D. W .Hawkins (dwh@ovro.caltech.edu) This 'basic' design configures the Arrow BeMicro-CV board so that it generated a count on the on-board LEDs. The design also attempts to disable the hard-IP DDR interface. However, Quartus must have a bug, as it hangs indefinitely in 12.1sp1, 13.0sp1, and 13.1 (see the commented sections of the code). The default version of the code compiles fine. Proceed as follows; 1. Unzip the source into c:/temp/bemicro_cv_basic/ 2. Start Quartus 3. Select the Tcl console (use View->Utility Windows->Tcl Console to make it visible if necessary) 4. Change to the source folder tcl> cd c:/temp/bemicro_cv_basic or using Windows style paths tcl> cd {c:\temp\bemicro_cv_basic} 5. Source the synthesis script tcl> source scripts/synth.tcl And the script will output messages ... Synthesizing the BeMicro-CV 'basic' design ------------------------------------------ - Quartus Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Full Version - Creating the Quartus work directory * C:/temp/bemicro_cv_basic/qwork - Create the project 'bemicro_cv' * create a new bemicro_cv project - Creating the VHDL files list - Applying constraints - Processing the design On this particular machine, Quartus 12.1sp1 ran out-of-memory. However, on my other development machine, the script works fine. 6. Download your BeMicro-CV. I plan on filing a Service Request regarding the failure to disable DDR. However, before I did that I wanted to get a DDR example working. Enjoy!   Cheers, Dave

[Altera_Forum]

I extended Tommy Thorn's git project to include a Nios processor and DDR3. 

 https://github.com/tommythorn/bemicro-cv     --- Quote Start ---  I give up: after much googling, I'm unable to find any starter Qsys-based projects for the BeMicro CV.  Is anybody aware of anything I might be overlooking?  I was hoping for NIOS+DDR3 Hard IP+PIO's for the switches/LED's, but right now it looks like I have to start from scratch with the .qsf assignments from the "ddr3_example".  --- Quote End ---  

[Altera_Forum]

Which reminds me, I was going to upload a new zip file with an improved basic example and DDR example. Read the readme.txt files in the respective example directories, eg., bemicro_cv/basic/readme.txt is 

  Arrow/Altera BeMicro-CV Development Kit --------------------------------------- 6/23/2014 D. W. Hawkins (dwh@ovro.caltech.edu) This 'basic' design blinks the LEDs on the development kit. To rebuild the design 1. Unzip the example source, eg., into C:\temp\bemicro_cv 2. Start Quartus 3. Select the Tcl console (if its not visible, select View->Utility Windows->Tcl Console) 4. Change directory to the top-level of the example tcl> cd {C:\temp\bemicro_cv\basic} 5. Source the synthesis Tcl script tcl> source scripts/synth.tcl The console will output the following messages ... Synthesizing the BeMicro-CV 'basic' design ------------------------------------------ - Quartus Version 13.1.4 Build 182 03/12/2014 SJ Full Version - Creating the Quartus work directory * C:/Temp/bemicro_cv/basic/qwork - Create the project 'bemicro_cv' * create a new bemicro_cv project - Creating the VHDL files list - Applying constraints - Processing the design - Processing completed 6. You can now use the built-in JTAG programmer to download the design.   The DDR readme.txt shows how to create the DDR instance, how to run the External Memory Interface Toolkit, and how to access the DDR via JTAG.  Cheers, Dave

[Altera_Forum]

Sorry to necro this old thread, but since my issues relate to both the BeMicro CV and the examples in this thread, I figured this would be the best place to post my issues. 

 I ordered a BeMicro CV about a month ago, and have been having no end of problems getting the DDR3 memory to work reliably with a Nios processor. I took Dave's code first, and tested the entire RAM area (with a little Tcl code) and everything works. I also designed a rudimentary VGA driver and powered it with a Nios CPU without any problems. But, for some reason, when the Nios CPU mates to the DDR3 UniPHY controller, the machine goes haywire. I've used Lemieux's example, plus made 3 or 4 separate designs of my own (worried that I might have screwed something up). It works fine for a few write/read test combinations, then the output stream become gobbledygook. Or it will just spontaneously halt. Or get stuck in a reset loop. I think the program memory is getting overwritten, but it still happens if the program memory is stored in a ROM (inside the Cyclone). I think I have defective hardware, but it's so strange that both the RAM and the chip seem to work perfectly, but they fail to work together. So I'm at my wits end. Thanks in advance for any input.

[Altera_Forum]

When things "don't work", the first thing you should do is to run the design in the Modelsim simulator. 

 Its not too hard to get the BeMicro-CV working with a DDR3 model. The BeMicro-CV hard-memory-controller has a bug in the resets. The code I posted here does not have the bug, but I submitted another zip file showing the issue as an Altera Service Request. Send me a direct email message (to my forum name) and I'll send you that zip file if you want it as a starting point.  It shouldn't be hard to get your design working in simulation. If the design simulates fine, but does not work in hardware, then at least you know the problem is not in the IP you are working with.  Cheers, Dave

[Altera_Forum]

Okay, turns out I had two problems. The first was the bug you mentioned, which I found detailed here (http://www.alteraforum.com/forum/showthread.php?t=40678), so there's no need for you to send the zip file. Thanks for the offer, though. The second was that the stack, heap, and text sections were being loading into DDR RAM, and since my program was writing to every byte of DDR RAM (to test the chip), it would end up overwriting my data. So that explains the "random" behavior. Now, everything is working and well behaved.