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Altera_Forum
Honored Contributor I
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BeMicro FPGA-based MCU Evaluation Board

This is the new BeMicro FPGA-based MCU Evaluation Board thread. Please post your questions and comments within this thread. Documentation and purchasing information can be found at www.arrow.com/bemicro (http://www.arrow.com/bemicro).

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84 Replies
Altera_Forum
Honored Contributor I
188 Views

I have installed my BeMicro. It works. 

I wanted to use an Intronix LA1034 Logic analyser too, and so the problems begin. 

They dont like each other. maybe because both are based upon ftdi and cyclone devices. 

Operating system: WinXP32,SP2 

 

the LA1034 just sits there if the BeMicro is configured, and can not be used, it freezes the analyser window. 

if the analyser was there first, then the Quartus 2 programmer freezes. 

 

bye, 

Martin
Altera_Forum
Honored Contributor I
188 Views

Hi, 

Was anyone able to get through the FPGA compilation of the Arrow lab on the "BeMicro Embedded System Lab"? I got to page 36, the part where the FPGA programming code is generated and got the message:  

 

Error: Can't generate netlist output files because the file C:/altera/kits/bemicro/bemicro_sopc_builder_lab/incremental_db/compiled_partitions/bemicro_lab_schem.root_partition.map.atm" is an OpenCore Plus time-limited file
Altera_Forum
Honored Contributor I
188 Views

I got through the lab without issue. Never saw any errors. I was using the web edition of the software on a Windows XP 32-bit laptop and no IP licenses. 

 

Jake
Altera_Forum
Honored Contributor I
188 Views

 

--- Quote Start ---  

Hi, 

Was anyone able to get through the FPGA compilation of the Arrow lab on the "BeMicro Embedded System Lab"? I got to page 36, the part where the FPGA programming code is generated and got the message:  

 

Error: Can't generate netlist output files because the file C:/altera/kits/bemicro/bemicro_sopc_builder_lab/incremental_db/compiled_partitions/bemicro_lab_schem.root_partition.map.atm" is an OpenCore Plus time-limited file 

--- Quote End ---  

 

 

I did not get any error like this. It was telling me during download that i need the time limited but thats because of the NIOS is not licenced (Quartus 2 web edition) 

Until i dont hit cancel on that "open core plus" window, it works correctly for me.
Altera_Forum
Honored Contributor I
188 Views

 

--- Quote Start ---  

Hi, 

Error: Can't generate netlist output files because the file C:/altera/kits/bemicro/bemicro_sopc_builder_lab/incremental_db/compiled_partitions/bemicro_lab_schem.root_partition.map.atm" is an OpenCore Plus time-limited file 

--- Quote End ---  

 

 

You don't need the netlist to complete the lab. As long as you get the time limited file to generate, then you are good to go.
Altera_Forum
Honored Contributor I
188 Views

To tanguerotom: 

 

It seems you have activated the EDA Netlist Writer without knowing. Select 

Assignments > EDA Tool Settings > Simulation 

and set the Tools name to <None>. This should help. 

 

Harald
Altera_Forum
Honored Contributor I
188 Views

I am using XP(32 bit) and Quartus 9.02 with the beMicro that I obtained at the workshop. 

 

When I get to the workshop step that involves the programmer, I don't see the beMicro USB blaster choice in the dropdown window. It just says No Hardware. When I first plugged in the bemicro it went through the driver installation as described and the devices appear in Windows Device Manager, but the programmer SW doesn't seem to find it. I repeated this on 2 other computers and got the same result. 

 

Has anybody had this problem and found a solution for it?
Altera_Forum
Honored Contributor I
188 Views

You skipped the part where you run the setup program. Read the instructions more carefully. You need to run a program that installs a DLL for the Arrow USB-Blaster driver. 

 

Section 1.5 on page 7 of the instructions. 

 

Jake
Altera_Forum
Honored Contributor I
188 Views

That certainly took care of that. 

Thank you.
Altera_Forum
Honored Contributor I
188 Views

Hello, i have a Problem with the BeMicro Board. 

 

Sry for my bad English. 

 

I have tryed to make the BeMicro Embedded System Lab Instructions, but on Step 5.1 where i should Insert the symbol "bemicro_system" from the project folder, there is no project folder in the symbol list! 

 

After this i have tryed to use the verilog instaed of the scheme file, if i do this i should on step 5.2 add the SDC Files CPU.sdc and bemicro_lab.sdc but the file CPU.sdc isn't in my project folder, i can't them find on my Harddisk. 

 

Without this Configuration Steps i can't compile my system! 

 

I have made all Steps befor correctly. 

 

Please Help me, it's very important! 

 

Thanks! 

 

Greetz
Altera_Forum
Honored Contributor I
188 Views

Hi all! I bought bemicro board last week,and I found that sram was not enough for my project .Now I want use IS62WV51216BLL not IS62WV25616BLL,but the datasheet of bemicro didn't give the pin number of A18, who can tell me what should I do ? 

Thanks!
Altera_Forum
Honored Contributor I
188 Views

Are there any indications that A18 is connected to the FPGA at all? If not, you could try to solder it to an expansion connector pin.

Altera_Forum
Honored Contributor I
188 Views

who can give me the linux driver of bemicro and schematic ? thanks!

Altera_Forum
Honored Contributor I
188 Views

I have the BeMicro and everything works well, including my own designs. However, I want to make the configuration permanent. 

 

I added the EPCS16SIBN device, cut the trace 1-2 at B400 and added a jumper 2-3. Pretty much just like the instructions. 

 

However, the built-in programmer is for JTAG and can not program the EPCS16 which is a serial device. 

 

What do I need to buy to be able to program the EPCS16? Will the FPGA then load directly from the EPCS16? 

 

Richard
Altera_Forum
Honored Contributor I
188 Views

You have to program the EPCS device indirectly through the FPGA. There are two methods for doing this: 

1 - Use the Quartus II programmer and create a JIC file. Then program the EPCS using the JIC file. What this will do is download a temporary image into the FPGA with enough intelligence to then program the EPCS. 

 

2 - Include the EPCS controller core in your SoPC system. Then with your FPGA image programmed into the FPGA, you can program the EPCS device with the nios2-flash-programmer. 

 

Jake
Altera_Forum
Honored Contributor I
188 Views

Jake, 

Thanks! It works perfectly! 

 

One last thing (well, probably not the very last), is there a way to get the FPGA to load from the flash without disconnecting and reconnecting to the USB port? I sure hope I didn't miss a check box or push button... 

 

Richard
Altera_Forum
Honored Contributor I
188 Views

You can use the remote update core. For Cyclone III there is a remote update controller in SoPC builder that allows you to reload the FPGA after changing the configuration. 

 

Jake
Altera_Forum
Honored Contributor I
188 Views

You have a Quartus Programmer option "Initiate configuration after programming" for this.

Altera_Forum
Honored Contributor I
188 Views

Found it! I just knew it was going to be something I overlooked. It's nice that the setting is sticky across projects. 

 

Thanks 

Richard
Altera_Forum
Honored Contributor I
64 Views

 

--- Quote Start ---  

Are there any indications that A18 is connected to the FPGA at all? If not, you could try to solder it to an expansion connector pin. 

--- Quote End ---  

 

 

I looked it up. A18 on a 512x16 part is the same as CE2 on the existing part. You should be able to drop in a 512x16 with no board modifications - but use the pin assigned to CE2 in the manual as A18 instead. 

 

I was looking at this part: 

http://www.issi.com/pdf/61-64wv51216.pdf but I believe that is part of the JEDEC spec.
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