BeMicro SDK MDDR controller

Altera_Forum · ‎07-03-2012

Arrow Europe offers a controller for the mobile low power SDRAM on the BeMicro SDK kit exclusively: www[/U][/U] arroweurope com/markets-solutions/solutions/bemicro/bemicro-sdk html.

However, I can find no information related to its use and the pdf that comes with it is vague. The download consists of verilog and an SDC timing file, the latter of which I am very unfamiliar with. I am sure that the timing constraints are incorrect, as I get the following error while trying to download software to the board.

Downloaded 20 KB in 0.3s (66.6KB/s)

Verifying 04000000 ( 0%)

Verify failed between address 0x4000000 and 0x4003597

The PDF has the follwing instructions for timing requirements:

After the controller has been added to an SOPC system the system must be generated. Then, before compiling the FPGA, the SDC file containing the timing constraints has to be adjusted. First, add the SDC file to the list of SDC files to be processed. Then use an editor to modify the data in the first section of the SDC file according to your needs. Detailed information about that can be found in the comment lines of the SDC file.

The first section of the SDC file is as follows:

# set the name of the PLL that sources the controller clock

set sysClock "nios2_bemicro_sopc_inst|the_pll|sd1|pll7"

# set the hierarchical path to the memory controller

set mddrInstanceHierName "nios2_bemicro_sopc_inst|the_mddr|mddr_ctrl"

# timing values

# set external clock cycle time

set t(ext_clk) 20.0

# address and control inputs timing requirements

set t(IS) 1.1

set t(IH) 1.1

# DQ and DM timing requirement in relation ton DQS

set t(DS) 0.58

set t(DH) 0.58

# max. and min. access window of DQ in relation to CK_N/CK_P for CAS latency of 2

set t(ACmax) 6.5

set t(ACmin) 2.0

# max. and min. board delay

set t(board,max) 1.0

set t(board,min) 1.0

# specifiy board delays

set t(board,CK_N) 1.0

set t(board,CK_P) 1.0

set t(board,LDQS) 1.0

set t(board,UDQS) 1.0

I don't know how to interpret this and would appreciate some help.

Thank you!

Altera_Forum · ‎10-26-2015

I'd like to second this question and add my own problems.

The mddr controller creates more pins then is in the sdc file. In particular mddr(d0-12) has pins for both input and output, while the sdc has simply one place for them. The same applies for LQDS and UQDS. I haven't been able to figure out which one is meant to be an input and which one an output.