FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
5922 Discussions

BeMicroSDK Nichestack Timer

Altera_Forum
Honored Contributor II
‎12-12-2011 08:54 PM
1,036 Views

The Qsys and or SOPC files for the BeMicro downloaded from various sources (example code from Microtronix and altera wiki superloop) have the high resolution timer set to 1us (processor running at 100MHz).  

 

Surely some mistake?
0 Kudos

Link Copied

2 Replies
Altera_Forum
Honored Contributor II
‎12-13-2011 06:32 AM
291 Views

That high-res-timer is used only for performance tests (e.g. bandwidth tests). The only required clock is system clock.

0 Kudos
Copy link
Altera_Forum
Honored Contributor II
‎12-13-2011 01:35 PM
291 Views

Thank you kindly.

0 Kudos
Copy link
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.