Hi everybody. I'm new to this board and to Altera development boards. And I have a question which probably has already been answered 1000 times in the past but I could not really find anything using the search function.For my new project I need an Altera FPGA development board for testing some high speed serial interfaces on another board. I did some research to find a good solution. I also found some boards that might be okay (considering the price etc.). But there is one big question: How do I communicate with the boards? How can I debug my designs? (ok, that's two questions). I need to read/write registers. I need to check memory contents. And since I'm dealing with high speed interfaces I need a pretty fast solution because there will be a lot of data to be checked. RS232 is not really an option. During my research I found that the Stratix V GX FPGA Development Board offers a way using the onboard USB Blaster. This USB Blaster can be used to either configure the device or to communicate with an Avalon memory mapped design using the System Console in Quartus II. Basically this is exactly what I'm looking for. However I'm wondering if this board is the only one offering this solution. I checked other boards (Stratix IV etc.) but their reference sheets do not mention another usage of the USB blaster besides the configuration. There is an Arria V board. It's reference sheet shows two ways of using the USB blaster in a picture but it does not mention it in the text. So I'm not really sure about this one. Bottom line it comes down to this question: If an Altera FPGA Development board has an onboard USB Blaster, can I use it to debug/configure my design using System console and Avalon? And while I'm at it: I need a board where some high speed transceivers of the FPGA have been connected to SMA connectors (at least 2). First I was taking a closer look at the Transceiver Signal Integrity Test boards but then I noticed the HSMC connectors on other boards and the daughter cards that can be used with them (one offers an entire array of SMA connectors). Do I understand it correctly that the high speed transceivers of an Altera FPGA are routed to these HSMC connectors so that (for example) buying the Stratix V GX FPGA development board + the daughter card with the SMA connectors would give me what I need?
Altera offers a number of debug solutions that work over the JTAG/USB-blaster interface.- SignalTap - In system memory editor - System Console - JTAG-UART - (maybe more?) These are available as long as your board has a JTAG/USB-Blaster interface.
Sounds good. I think I would prefer the System Console <=> USB Blaster <=> Avalon solution. Can any board with a USB Blaster do this (with the only difference that the USB Blaster II is much faster) or is a USB Blaster II being required?
Hi there,I'm about to implement my design in Qsys. So far I like this tool, but after some succesfull playing-around, I'm now stuck with a problem I can't figure out. First let me explain, what I wanna do: Our company has developed an ASIC with several highspeed interfaces. In order to test these interfaces we want to use a FPGA board. This board will contain one of those interfaces which we will connect to the ASIC. So the configuration looks like this PC (with Qsys) <=> USB cable <=> USB Blaster II <=> USB Debug Master <=> Avalon <=> AXI Master <=> Interface with AXI Slave <=> ASIC I want to simulate the design with Qsys (register accesses to the interface etc.). Therefore I have turned the interface into a Qsys component. This went pretty well. But now I'm at the point where I need to connect the USB Debug Master with the AXI interface of my component. And I can't figure out, how to do this. As far as I see this, I need something that converts the Avalon protocol from the USB Debug Master into AXI master signals which I can connect to my AXI slave interface. I looked at every AXI component available in Qsys but there is nothing that fits my requirements. I also checked this board and the Altera Support but I could not find an answer. The AXI Slave Agent which provides an AXI master interface has some streaming ports I don't now how to handle. The Qsys Interconnect manual mentions the Memory Burst Adapter without getting too specific. It's quite a puzzler. Does anyone have experience with this issue? I'm pretty sure I'm not the first one trying to create an AXI connection in Qsys.
I think QSYS will automatically insert the right components to connect an Avalon MM master to an AXI slave. The slave agent component (with the streaming interfaces) is one of the components which is inserted by QSYS to do this.Are you able to connect the USB debug master to your slave in the patch panel? If you want to simulate (eg in Modelsim) then the JTAG Avalon Master component in 13.1 has simulation support so in your simulated design you can replace the USB Debug Master with this. The two components are equivalent functionally, but the USB debug master is quite a lot faster in hardware.
Thanks. :)I didn't think of that. I somehow couldn't believe that Qsys would allow me to just connect two completely different interfaces and then add the required translation hardware automatically.
And here we go again...In the test design I created to play around with Qsys I needed an AXI master interface exported to the entity of the component. I tried every AXI component available in Qsys. But the only component offering an AXI master interface that can be exported is a streaming component (Altera Axi Slave Agent) and I cannot connect this component to the Avalon MM Pipeline bridge. I also tried to add one of the available streaming interfaces but they have two streaming ports (read_cp and write_cp) and I can connect only one to the bridge. In my test design I finally ended up with importing my AXI slave component into Qsys. Then I connected the AXI slave interface to the Avalon MM bridge. So I got a workaround for this problem. But is there any way to export an AXI master interface to my Qsys component that is connected to the Avalon MM Bridge? Basically I want this: | USB Debug Master <=> Avalon MM Bridge <=> AXI Master Interface (exported) | <=> My component outside of Qsys with AXI slave interface
The easiest way to do this is to build a component with an AXI master and an AXI slave, you can use the debug.driven_by property to link the ports together so you don't need any HDL. A simple example in the 13.1 library is altera_clock_bridge (ip/altera/merlin/altera_clock_bridge/altera_clock_bridge_hw.tcl)Once you have such a component you can use it to constrain the memory mapped port to be the correct shape for your component - you can put it into your system in place of the Avalon MM bridge in your post above and export its master interface.