Bemicro SDK 80 I/O pins from edge connector

[Altera_Forum]

Hi, 

 I would like to know how is the compiled .SOF file provided in the lab material uses the 80 pins edge connector. Because i can see that, Eclipse IDE recognizes 2 32bits GPIO being used in the SOPCinfo file. So i would like to know which GPIO pins correspond to which physical edge connector pins.  The main reason why i wanna use the compiled .SOF they provided is because, the ridiculously expensive Mobile DDR memory IP core you need to buy in order to recompile the design if you wanna use the SDRAM onboard. Without the SDRAM, the Bemicro SDK is pretty much USELESS.. So someone please shed me some light before i throw this thing away..   Thank you.  Regards, Michael

[Altera_Forum]

--- Quote Start ---   I would like to know how is the compiled .SOF file provided in the lab material uses the 80 pins edge connector.   --- Quote End ---  You'd have to look at the pin assignments for the project, and then compare that to the schematic. Page 7 of the schematic shows that there are GPIO pins P1 to P60 connected to the 80-pin connector.  There's a good chance the 32-bit GPIO ports are mapped to 1-32, and 33-60.    --- Quote Start ---   Without the SDRAM, the Bemicro SDK is pretty much USELESS.   --- Quote End ---  Useless for projects that need the SDRAM, but not entirely useless :)  Why not download the evaluation version of the controller (from whoever it is that supplies it)?  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  You'd have to look at the pin assignments for the project, and then compare that to the schematic. Page 7 of the schematic shows that there are GPIO pins P1 to P60 connected to the 80-pin connector.  --- Quote End ---    I've tried that, non of them are configured to be output, all inputs...    --- Quote Start ---   Useless for projects that need the SDRAM, but not entirely useless :)   --- Quote End ---  Which means i cant really use NIOS2 design... such a nicely designed FPGA, what a waste.:(    --- Quote Start ---   Why not download the evaluation version of the controller (from whoever it is that supplies it)?   --- Quote End ---  Tried that too.. they will only allow you to use it for 1 hour everytime you compile.  I would much rather get a Terasic DE0-nano than Bemicro Nano, since they provide important IP cores. I found out, i could actually use the SDRAM controller that comes with SOPC builder, just a little timing configuration.   Michael

[Altera_Forum]

--- Quote Start ---  I've tried that, non of them are configured to be output, all inputs...   --- Quote End ---    Your original question did not mention you cared about the direction. That would be a function of the SOPC system.    --- Quote Start ---   Which means i cant really use NIOS2 design... such a nicely designed FPGA, what a waste.:(   --- Quote End ---    Yep, I agree that it was a bad choice to select a memory that was not directly supported by Altera's IP.    --- Quote Start ---   Tried that too.. they will only allow you to use it for 1 hour everytime you compile.    --- Quote End ---    That is a pain.    --- Quote Start ---    I would much rather get a Terasic DE0-nano than Bemicro Nano, since they provide important IP cores. I found out, i could actually use the SDRAM controller that comes with SOPC builder, just a little timing configuration.   --- Quote End ---     The Terasic boards are all good.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  spam  --- Quote End ---     Dude.. the forum is for professional use only. no ads!

[Altera_Forum]

Where did you find a reference design for the pins ?

[Altera_Forum]

--- Quote Start ---  Where did you find a reference design for the pins ?  --- Quote End ---    The schematics.  Here's my constraints file (download and rename it to constraints.tcl).  Cheers, Dave