Bidirectional IO connected to FPGA fabric on Cyclone V SOC Dev. Kit

[martinonorcas]

I have a Cyclone V SoC Dev. kit.  (DK-DEV-5CSXC6N)

Which has a 5CSXFC6D6F31 Cyclone V FPGA

I need to connect my own I2C slave-only controller implemented in the FPGA fabric to a couple of pins accessible on the Development Board. From what I can see all of the available GPIOs are on the HSMC debug breakout header.  All of the available pins seem to be unidirectional TX or RX . I need the SDA to be bidirectional. Is there a pin on the board I can connect to the FPGA fabric that can be bidirectional?

My only way to trace the connections is via the Schematic.

What document can I use to make the specific IO pads on this FPGA device to their type??

And look up the functionality of that IO pad.

Thanks Martin

[AqidAyman_Intel]

Hello,

You can refer to the pinout file for the respective device that you used, for example this case is Cyclone V. Refer link below:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/lit-dp.html

For each type of the pin description and guidelines, you can refer to link below:

https://www.intel.com/content/www/us/en/content-details/654351/cyclone-v-gx-gt-e-sx-st-and-se-device-family-pin-connection-guidelines.html?DocID=654351

[FvM]

Hi,
except for a few dedicated clock signals and Gigabit transceiver signals, none of the HSMC connected FPGA pins is unidirectional. You'll see if you study the pin list. It's just the case that HSMC standard assigns directions to specific pins.

Regards
Frank

[AqidAyman_Intel]

I afraid there is no bidirectional pin available in the HSMC since it is mentioned that the port has x4 transceivers, x16 TX LVDS, x16 RX LVDS as in the web page: Cyclone® V SX SoC Development Kits (intel.com).

I tried to check on HSMC interface of MAX 10 User Guide, and it mentioned that the interface has programmable bi-directional I/O pin. Refer below:

https://www.intel.com/content/www/us/en/docs/programmable/683460/current/hsmc.html

I am not quite sure if it is the same case for Cyclone V SoC Dev. Kit.

However, I can suggest you refer to this documentation for details on the HSMC specification:

https://cdrdv2.intel.com/v1/dl/getContent/655196

[AqidAyman_Intel]

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