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Hi,
I have to use a FSBL (First Stage Bootloader which is a .hex file) in order to boot up my HPS correctly according to the guide "Intel Agilex-7 SoC FPGA Boot User Guide". I couldn't find any prebuild .hex FSBL for my board that is why I have tried to use another prebuild one for DK-SI-AGF014EA from the RocketBoards.org. I used u-boot-spl-dtb.hex. Then I combined my .sof with this .hex and generated another .sof then converted it to .jic and programmed my QSPI flash using Quartus Programmer Tool. At least in this scenario, programmer detects my HPS in Jtag Chain. But the boot fails as seen in "SerialTerminal.PNG" attached to this post. I also tried to use the Uart0 peripheral and it gave me the error as seen in "jtagConsole.PNG" attached to this post. I accept these errors because the FSBL that is used for this board is not generated for this board so the results are quite acceptable. Then, I compiled a simple app that writes a message to console using puts(). I downloaded this code firstly to the OCRAM and secondly to the SDRAM using a .scat file I tried both and It worked without any problem. So, I guess the problem is u-boot wants to use uart0 to print its own messages and at the same time If I want to use that peripheral in my code there occurs a problem. Because U-boot fails to boot from any device so it continuously prints messages to uart0 terminal and never releases it. In this scenario, I need to find an appropriate FSBL for my board or generate it myself but I don't know how to do it and I couldn't find any quide for my board. Could you please help me about that?
Best Regards,
Balerion
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hello, please refer to this link for gsrd: https://altera-fpga.github.io/rel-24.3/embedded-designs/agilex-7/f-series/soc/gsrd/ug-gsrd-agx7f-soc/#prerequisites
rgards,
Farabi

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