FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
5892 Discussions

Boundary-Scan Testing in DE0/DE1

Altera_Forum
Honored Contributor II
855 Views

Hi, 

 

How do you do a boundary-scan testing in a DE0/DE1 board? Is it even possible? I cant see any separate JTAG pins 

 

Thanks 

Arjuna
0 Kudos
0 Replies
Reply