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Altera_Forum
Honored Contributor I
1,800 Views

C4GX kit dev + TSE without external memory

Hi all,  

 

I got a new mistake. 

I start with the board update portal design from altera. 

 

I don't understand why in this design there is a big onchip memory and SSRAM. 

Can someone explain me how does it work. 

 

Is the code loaded in the onchip memory to the SSRAM?  

The SGDMA's are writting directly to the big onchip memory or SSRAM ?  

 

I would like to modify it and use the design without external memory. 

 

But I try to had an onchip memory to replace the SSRAM. 

But It doesn't work. 

In SOPC in NIOS I've got the vector interruption adresses at my onchip memory adress + 0x120 offset. 

 

My hex files from nios SBT is 379 bytes larger. 

 

I would like to have an exemple of SOPC configuration and BSp linker adresses (SBT tools). 

 

 

 

I'am lost. 

 

Thanks for help.
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13 Replies
Altera_Forum
Honored Contributor I
83 Views

Hi,  

 

I've got something new. 

In SOPC I add an onchip memory named onchip_ssram (@ auto assigned at 0x00080000 to 0x00098fff). 

 

I connect this memory to instruction master and data master (nios) and sgdma_rx.m_write and sgdma_tx.m_read. 

 

I set in cpu, exception adresse to onchip_ssram + offset 0x120. 

 

Build it, compile. 

 

Go to SBT refresh, generate BSP and debug. 

 

The program start but break at : 

 

alt_u8 alt_avalon_sgdma_do_sync_transfer( 

alt_sgdma_dev *dev, 

alt_sgdma_descriptor *desc) 

 

… 

… 

… 

… 

… 

 

/* Wait for the descriptor (chain) to complete */ 

while ( (IORD_ALTERA_AVALON_SGDMA_STATUS(dev->base) & 

ALTERA_AVALON_SGDMA_STATUS_BUSY_MSK) ); 

 

… 

… 

 

in the file altera_avalon_sgdma.c 

 

It wait for sgdma not busy ???  

 

 

Someone got an explication or idea. 

 

Thanks.
Altera_Forum
Honored Contributor I
83 Views

Hello, 

I used stratix ive developmental board, and the fpga (ep4se530k......) is having lot of internal memory. So, I configured onchip memory of size 128kbytes (not bits). please check the memory size required for SSS application. If it is morethan onchip memory size, increase the onchip memory size, so that application can be loaded.
Altera_Forum
Honored Contributor I
83 Views

The SSS application requires around 379 Kbytes and my on-chip memory is 512 Kbytes. 

 

In Sopc builder I've got exception vector to on-chip memory + offset (0x120). 

 

In BSP file, I configure in the linker .bss, .rwdata .text .rodata .heap .stack to the on-chip memory. 

 

Maybe my memory is not enough big?
Altera_Forum
Honored Contributor I
83 Views

Hello, 

According to ur reply memory is not the problem. Here I am furnishing working SOPC Screen Shot, Please look at.
Altera_Forum
Honored Contributor I
83 Views

Thanks for the picture but I can't see anything it's too small. 

 

I found something interresting, the sgdma's (rx and tx) are connected to the uas port of the ssram and ext_flash. 

 

I've started this test with the original project. I disconnect rx and tx sgdma from ext_flash. 

Recompile and test ----> don't work and stuk like usual (wait descriptor chain). 

 

I go back to Qsys and make ctrl+z to have my connection restored. 

Recompile and test ----> don't work too, same problem. 

 

Interresting. 

I investigate.
Altera_Forum
Honored Contributor I
83 Views

Hi, 

I am sending sopc screenshoot in pdf format as an attachment, please look at.
Altera_Forum
Honored Contributor I
83 Views

Thank you very much, It could be helpfull.

Altera_Forum
Honored Contributor I
83 Views

hi, 

I have the same problem... my program stall at 

/* Wait for the descriptor (chain) to complete */ while ( (IORD_ALTERA_AVALON_SGDMA_STATUS(dev->base) & ALTERA_AVALON_SGDMA_STATUS_BUSY_MSK) ); 

 

I work on a cycloneIII 3c120 demoboard, the sopc is about the same as kmk_drdo's has posted; but I haven't so much on-chip-ram so I use an external ssram (which work with other app). 

 

any hints to solve the problem? 

 

Ale.
Altera_Forum
Honored Contributor I
83 Views

Are you sure that the Ethernet driver is using the descriptor_memory to store the descriptors? As the SGDMA's descriptor masters are only connected to that memory, the DMAs will freeze if you try to use them with descriptors in main memory.

Altera_Forum
Honored Contributor I
83 Views

hi, daixiwen 

sorry but it's my first experience with ethernet so I don't know how check if ethernet use the descriptor memory... 

I found in the file tse_my_system.c the following code 

alt_tse_system_info tse_mac_device = { TSE_SYSTEM_EXT_MEM_NO_SHARED_FIFO(TSE_MAC, 0, SGDMA_TX, SGDMA_RX, TSE_PHY_AUTO_ADDRESS, &marvell_cfg_rgmii, DESCRIPTOR_MEMORY) }; 

has something to do with that you say?:) 

 

PS: I'm using the simpleSocketServer (RGMII) application example project as base and the custom SOPC shown in previous post. 

 

thanks 

 

Ale.
Altera_Forum
Honored Contributor I
83 Views

It looks like it's setup properly... it could be a good idea to put some Signaltap probes all around the SGDMA to check up what it is doing.

Altera_Forum
Honored Contributor I
83 Views

Hi all,  

 

I was very busy and know i can share you my little experience. 

I ask to the altera support and the response is not very accurate. 

 

In according to altera support is better to don't use QSYS and when you start from an design example to don't modify the SOPC system even if you don't use some peripherals. 

 

For me it works but the response it is not what I expect. 

 

thanks.
Altera_Forum
Honored Contributor I
83 Views

Well I'd say that answer from Altera support isn't the best way to promote QSys :)

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