thank you for your answer .
I was wrong with the designator of the connector in the CYCLON 10 LP evm for GPIO HEADER , the designator it J10 not JP13. but I think that your answer will be the same . am I correct?
ofer israel adam
Yes you are correct, I was able to understand that Question was related to cyclone 10LP evaluation kit and GPIO designator J10 was typo mistake.
All GPIO signals GPIO[0:35] are 3.3V single-ended LVCMOS/LVTTL signals who are connected to Intel Cyclone 10 LP FPGA directly. hence we can't use it as LVDS pin.