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Valued Contributor III
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CII DSP kit audio examples using DSP Builder

I made a sample driver for TLV320AIC23 Stereo Audio CODEC chip which is mounted on CII DSP kits in Verilog-HDL. I attach the files with two very simple DSP Builder projects. 

sound_basic_dspb\sound_basic.mdl : just take in analog Line-In input and send it on Line Out/Headphone output. 

sound_echo_dspb\sound_echo.mdl : add delayed echo to Line-In input and send it on Line Out/Headphone output. 

 

To play with them: 

1. open aic_audio HDL import block and push compile (after compilation, the HDL import block shrinks up, please extend down the block size). 

2. Compile and Program from Signal compiler.  

 

Both examples are for 2C70 kit. Sound_basic.mdl runs on 2C35 kit with just replacing the board block. On the other hand, since sound_echo.mdl uses some amount of M4K as delay FIFO, you have to reduce the FIFO size arund half in delay_echo_L/R block for 2C35. 

 

Remark: To set the pin assignments of the codec chip, I used *_add_user.tcl.
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Valued Contributor III
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Hi EOFZ, 

I have downloaded and use your excellent codec interface files. 

It works properly on EP2S60 DK and all I had to do was pins assignment. 

I analyzed your code and simulink model . 

I don't understand the logics of synchronizing clocks. 

BCLK = 40MHz /16 and SCLK 40MHz/32 . 

Following your registers mapping the interface works in USB clock mode i.e. 12MHz . 

After I changed Sample Rate Control Register to 8 Khz input and output the results I received were the cut off 6KHz which means 12Khz sample rate. 

I'll really appreciate your help. 

yan_w
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Valued Contributor III
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Hi yan_w, 

 

Thanks for having interest in my little example :)  

 

If you want to change the audio sampling frequency, you also need to modify the frequency of dec_adc_valid signal(=en_40K).  

 

With 40MHz system clock, generated clocks are following: 

BCLK = 5 MHz (40/8) 

SCLK = 2.5 MHz (40/16) 

MCLK = 10 MHz (40/4) . 

I set the sample rate control register of the codec as USB mode, as you mentioned, which assumes that MCLK is 12MHz. But MCLK is 10MHz in this design. Under this settings, the audio sampling frequency results in 40KHz (48KHz* 10/12). If you need a standard sampling frequency(8K, 32K, 44K, 48K, 88K, 96KHz), please feed 48MHz system clock instead of 40MHz. You may select 48MHz PLL output if you use Stratix II. 

 

To realize 8KHz sampling in breaf: 

1. Change system clock freq into 48MHz. 

2. Change en_40K freq.  

Line 38 of aic23_audio_clken.v should be  

reg [12:0] cnt1000; 

Line 44 of aic23_audio_clken.v should be  

If (cnt1000 == (6000-1)) 

3. Modifiy sample rate control register setting. 

 

I hope this works…
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Valued Contributor III
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Its help. 

Thank you very much .
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Valued Contributor III
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Hi EOFZ, 

i have a 2C35 board and i tried to implement your code in it, but it is not working. I think the problem lies in the pin assignment. I don't know which fpga pins should I assign to CSN and Mode. Also, should I assign i2c_sclk and i2c_sdat to sclk and sdin respectively? please help.... 

 

Omee
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Valued Contributor III
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Hi Omee, 

So sorry my slow response. 2C35 board and 2C70 board have identical pin assignments. CSN is PIN_AC25. 

The example uses SPI mode for control interface. What do you mean i2c_sck and i2c_sdat? I think the design does not have such signals… 

 

EOFZ
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Valued Contributor III
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hello EOFZ, 

thanks for your kind reply. 

 

I could not, however, agree with you about the pin configurations of 2C35 and 2C70 board. I've attached the pin configuration file with this mail, can you please compare it with 2C70's pin configuration file? (I could not get that file from anywhere :( ). 

 

Can you please tell me which pins i should connect, and where? 

 

thanks in advance.
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Valued Contributor III
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Hi Omeecd, 

 

I’ve misunderstood your environment. I assumed that you had 2c35 DSP kit. But your board is DE2 board. Yes, DE2 do have different pin assignments than 2c70/35 DSP kit. 

 

I reviewed DE2 schematic and found my example mdl/Verilog is not compatible with DE2 board, unfortunately. I assume that the audio codec chip can be accessed in 3-wire mode for the control register interface. But MODE pin of the codec chip is tied to GND in DE2 board. This means that you must communicate with the codec chip through 2-wire(I2C) mode in DE2 board.  

 

You need to change pin assignments and modify the design to talk with the codec chip via 2-wire interface for DE2. The main code to be modified is HDL/aic23_avalon_mm_ctrl.v. I think the DE2_i2sound demo source code attached with DE2 is helpful as a start point. 

 

I can not promise the time line, I may modify my code to support I2C interface…. 

 

EOFZ
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Valued Contributor III
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EOFZ,  

can you please help me out with this problem too: 

http://www.alteraforum.com/forum/showthread.php?p=20596#post20596 

 

thanks.
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Valued Contributor III
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thank you very much for the confirmation. I've already tried to control the audio codec using I2C. Please check the link i've given. I'll be glad to have any suggestion. 

 

thanks :)
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Valued Contributor III
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Hi Omeecd, 

 

I posted DE2 version of designs having I2C interface at  

http://www.alteraforum.com/forum/showthread.php?t=5167 

 

I hope this works for you ;)
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Valued Contributor III
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WOW!! This is truly wonderful!! Thanks a lot my friend! I was really lost with my code and couldn't figure out what the problem was..... i haven't tested your code yet though.... i will write you again when i have finished testing. 

 

:)
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Valued Contributor III
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COOL!! the file is working just fine! I've changed the configuration parameters and tested the outcomes.... they are just perfect!! 

 

ThanK You EOFZ for helping me!! :)
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Valued Contributor III
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EOFZ, you made a sample driver for TLV320AIC23 Stereo Audio CODEC chip which is mounted on CII DSP kits in Verilog-HDL.  

But i´m missing the MIC-in. Pls, can you help me?
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Valued Contributor III
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Hi friends!....i have a question on the driver for TLV320AIC23 Stereo Audio CODEC by EOFZ, it's possible yet?? 

Thank you
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