I'm testing the error detection and recovery functionality of a Max10 board.
I injected it with the Jtag cable, by run a .jam file as shown in the AN-539 procedure related to the CRC code test methodology found at page 25.
When the script gets executed, the CRC err pin goes HIGH as it should be. Next, I pull low the NCONFIG pin to reset the Max 10.
The FPGA correctly reconfigures itself but after the reconfiguration time the CRC ERROR pin does not get low as expected. It remains in a HIGH state.
Why is this behavior happening? is it due to the fact that I injected the error with the Jtag cable? with a real world SEU the behavior would be opposite with the CRC low or the same?
Just would like to understand further, so the JAM file you are programming is intended to cause CRC error?
Then at first, with the CRC error injection, the CRC error pin goes HIGH. Then after reconfiguration, with the CRC error injection, the CRC error pin does not go HIGH?
Also, is the image the same between both initial bootup image and reconfiguration image?
with the CRC error injection, the CRC error pin goes HIGH correctly, but when I pull the nConfig pin LOW and then HIGH to reset the fpga I expect that the CRC err goes LOW but it remains HIGH instead.
the image after reconfiguration is the same.
Sorry for being late as i was checking with expert about this. By right it should be unless there is a real CRC error occur.
Probably you can try to disconnect the JTAG and see if it is really causing the problem.