CYCLONE V SOC上FPGA加载后需要复位CPU才能正常访问外部SDRAM

[AWu6]

FPGA需要通过H2S访问HPS的SDRAM，FPGA是HPS通过FPP32完成配置，但是配置完FPGA之后，FPGA通过H2S访问HPS SDRAM没有任何响应给FPGA，这时只有复位下cpu（clod Reset 或者 warm reset 都可以）， 复位cpu后，FPGA读写外部sdram就恢复正常。 要是再重新加载FPGA，还是要复位CPU一次FPGA才能正常读写外部SDRAM.

请问一下，这个可能是什么原因导致的？

[Fawaz_Al-Jubori]

Hello,

I would like to know how are you going to read the SDRAM from FPGA? do you have Nios II?

Probably you need to make sure the bridges are enabled, so that you can access freely.

Make sure you run this in uboot:

run bridge_enable_handoff

the command above will enable the bridges.

Are you using a dev kit? I might be able to send you a working design if you would let me know which dev kit are you using.

Thank you