This question is about the eMMC read and write speed of the Cyclone V and the Arria 10 (SoC FPGA's). Both specify 8 bits wide and a clock of 50 MHz. There is also a mention of a 25 Mbytes/sec speed of the Cyclone V and a 50 Mbytes/sec speed of the Arria 10. On an Arria 10 development board we were able to demonstrate the 50 Mbytes speed because it had an eMMC part on the board. On our own Cyclone V board we could only achieve 20 Mbytes/sec. Both were using Lynx but likely not the same version.
If they both do 8 bits wide and run a 50 MHz clock, why wouldn’t they both do the 50 Mbytes/sec?
Note that on our board we tried to match the trace lengths of the signals for the eMMC. We did have a layout issue with bit 4 trace not matched. We have respun the board for a different issue and we corrected the trace. Soon we will have updated boards.
Would be good to have something closer to 50 MB/sec on Cyclone V.
Would like an answer about the true performance limits of the Cyclone V. There appears to be conflicting specs from the datasheet.