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Can I use GXB PIN of Stratix 10 as a pure data line?

WKUAN
Novice
452 Views

Hello,

Can the GXB pin be used as a pure high speed data line using 28GSPS NRZ without any protocol? for example, I wish to send 010010001010... out from one of the GXB differential pair, and the data code can be controlled by the verilog code.

When I compile the code with quartus, i get the following error info. I seems that i can not assign the GXB pin as a output pin?

 

Below is my code.

module m28GSPS(clk,rst,test);
input clk,rst;
output reg test;

always @(negedge rst or posedge clk)
begin
if(~rst)
begin
test <= 0;
end
else
begin
test <= 1;
end
end
endmodule

 

Below is the error

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175020): The Fitter cannot place logic pin in region (0, 31) to (0, 31), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): test
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (184016): There were not enough differential output pin locations available (1 location affected)
Info (175029): pin containing PIN_D4
Info (175015): The I/O pad test is constrained to the location PIN_D4 due to: User Location Constraints (PIN_D4)
Info (14709): The constrained I/O pad is contained within this pin
Error (12289): An error occurred while applying the periphery constraints. Review the offending constraints and rerun the Fitter.
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:10
Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

 

 

Thanks and best regards,

0 Kudos
9 Replies
Ash_R_Intel
Employee
437 Views

Hi,

I was able to assign the pin to GXB pin by assigning IO standard as High Speed Differential IO. Attached is the design.

 

Regards

WKUAN
Novice
431 Views

Thank you very much, I have download the file, and get this error when i try to open the project 

Info: Running Quartus Prime Shell
Info: Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition
Info: Processing started: Fri Aug 20 13:43:22 2021
Info: Command: quartus_sh --restore -output G:/PROJECT/28GSPS/xvcr_bypass_21_1_0_169_restored/ -no_overwrite G:/PROJECT/28GSPS/xvcr_bypass_21_1_0_169.qar
Info: Quartus(args): -unqar -output G:/PROJECT/28GSPS/xvcr_bypass_21_1_0_169_restored/ -no_overwrite G:/PROJECT/28GSPS/xvcr_bypass_21_1_0_169.qar
Info: qar.tcl version #1
Error: Failed to restore G:/PROJECT/28GSPS/xvcr_bypass_21_1_0_169.qar
Error (23031): Evaluation of Tcl script c:/intelfpga/16.1/quartus/common/tcl/apps/qpm/qar.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 2 errors, 0 warnings
Error: Peak virtual memory: 4804 megabytes
Error: Processing ended: Fri Aug 20 13:43:24 2021
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:02

Have I lost any file?

 

Ash_R_Intel
Employee
429 Views

You are trying to open the file in 16.0 Std version, whereas the file I attached is for 21.1 Pro version. If you don't have this version, you can send me your minimal design and I will try to fix it here.

 

Regards

WKUAN
Novice
427 Views

Thank you, I have created the file with cyclone V GX, because by now i have not installed the stratix 10 device, though i might use stratix 10 in the next project. is the GXB function similar between cyclone and stratix despite of the speed? 

Ash_R_Intel
Employee
413 Views

Hi,

There is a difference in the Cyclone V and Stratix 10 transceiver architectures:

In Cyclone V we cannot bypass the serdes logic whereas in S10 we can. Compare the screen shots below. 

S10:

Ash_R_Intel_0-1629450414651.png

 

Cyclone V:

Ash_R_Intel_1-1629450488902.png

 

So it is not possible to implement what you want to, in Cyclone V.

 

Regards

WKUAN
Novice
409 Views

Thanks, it is good news, actually I want to do this with S10, so I will download high version quartus for evaluation. 

 

WKUAN
Novice
367 Views

Hi Ash_R_Intel, 

I have downloaded V21.2 from intel website, after installing Quartus, it is great to find that the GXB pin can be assigned as high speed differential IO,  thank you.

Now I want to know if I can use the GXB pin like nomal LVDS pins with some kind of IPcore, since when I use lvds_tx ipcore, it is able to work no more than 1.4G, but i want to produce 28GSPS plain signal (only 0,1bit, without any kind of coding format,even 8-10 coding or 64-66 coding) with GXB, is there any kind of ipcore to do this job?

 

Ash_R_Intel
Employee
335 Views

Hello,


The deserializer bypass is supported through the GPIO Intel® FPGA IP.

https://www.intel.com/content/www/us/en/programmable/documentation/sam1439794388346.html#sam14034823...


Regards


Ash_R_Intel
Employee
104 Views

We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


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