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Jiayi_H_Intel
Employee
234 Views

Can LVDS clock pin be assigned to general differential IO?

Hi experts,

 

We are using LVDS with internal PLL, on 10M50 board. Is there a hard requirement that LVDS tx/rx clock pin should be assigned to a dedicate clock pin?

Is there any violations or bad impact if we assigned it to general differential IOs?

I got such error if I assigned it to general differential IO pin. Is there any workaround for it?

Error (176554): Can't place PLL "ioc_top:ioc_top_inst|lvds_rx:lvds_rx_inst|altera_soft_lvds_rx_sXRJHsuO:lvds_rx_inst|lvds_rx_pll" -- I/O pin lvds_clk_in (port type INCLK of the PLL) is assigned to a location which is not connected to port type INCLK of any PLL on the device

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3 Replies
124 Views

Hello there ,

Can it possible to share the design to look at in details ?

 

Thank you ,

 

Regards,

Sree

Jiayi_H_Intel
Employee
124 Views

Here is the example module instantiate LVDS:

module top (

input     lvds_clk_in,

output     lvds_clk_out,

    input     lvds_rx_in,

    output     lvds_tx_out

    );

 

lvds_rx lvds_rx_inst (

  .rx_inclock      (lvds_clk_in),  //  rx_inclock.rx_inclock

  .rx_in         (lvds_rx_in),     //     rx_in.rx_in

  .rx_out        (lvds_rx_data),    //    rx_out.rx_out

  .rx_data_align     (bit_slip_sync2), // rx_data_align.rx_data_align

  .rx_outclock      (rx_outclock),  //  rx_outclock.rx_outclock

  .pll_areset      (!lvds_rstn),  //  pll_areset.pll_areset

  .rx_locked       (rx_locked)   //   rx_locked.rx_locked

);

 

lvds_tx lvds_tx_inst (

  .tx_in         (lvds_tx_data),    //    tx_in.tx_in

.tx_out        (lvds_tx_out),    //   tx_out.tx_out

  .tx_outclock      (lvds_clk_out), // tx_outclock.tx_outclock

.tx_coreclock     (tx_coreclock), // tx_coreclock.tx_coreclock

  .tx_inclock      (clk_100_max10), // tx_inclock.tx_inclock

  .pll_areset      (!lvds_rstn), // pll_areset.pll_areset

.tx_locked       (tx_locked) 

);

 

endmodule

 

Here is pin assignment with Good/Bad assign, Device : 10M50DAF484C6GES

 

#hsmc_clk_in =============== Good Pin assignment

set_location_assignment PIN_V10 -to lvds_clk_in

set_location_assignment PIN_V9 -to lvds_clk_in(n)

 

#hsmc_clk_in =============== Bad Pin assignment

#set_location_assignment PIN_W6 -to lvds_clk_in

#set_location_assignment PIN_W5 -to lvds_clk_in(n)

 

 

#hsmc_clk_out

set_location_assignment PIN_W8 -to lvds_clk_out

set_location_assignment PIN_W7 -to lvds_clk_out(n)

 

#hsmc_rx

set_location_assignment PIN_V5 -to lvds_rx_in

set_location_assignment PIN_V4 -to lvds_rx_in(n)

 

#hsmc_tx

set_location_assignment PIN_W3 -to lvds_tx_out

set_location_assignment PIN_W4 -to lvds_tx_out(n)

 

124 Views

Looks like Pin V9 and V10 is dedicated clk input , whereas W5 and W6 is not . PLL inclk should be from the dedicated clk pin.

You can try to use the altclkbuf cntrl ip option. This might help to connect the non-dedicated input clk pin to clk tree in the FPGA.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altclock.pdf

 

Thanks

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