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Altera_Forum
Honored Contributor I
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Can't generate 20Mhz clock from Cyclone III Starter Kit

I'm using the Cyclone III Starter Kit along-with some ADC & DAC chips. These chips demand a 20 MHz input clock, which I intend to generate from my Starter board. 

 

After going through the "my_first_fpga_tutorial" - it seemed quite simple to me : Just have an ALTPLL megafunction generate the 20 Mhz output from the 50 Mhz clock input. (osc_clk: Pin_V9) 

 

I tried that, and assigned the generated output clocks to the "HSMC_CLKOUT_n2" & "HSMC_CLKOUT_p2" pins (they are dedicated clock output pins I guess) 

 

I used the same code for the TimeQuest SDC file, as is given in the tutorial (since i've yet to learn what this is): 

create_clock -period 20.000 -name osc_clk osc_clk 

derive_pll_clocks 

derive_clock_uncertainty 

 

Now I test the corresponding output pins on the oscilloscope, but all I see is a very jittery signal (can't trigger it stable on the scope by any means), with a very low frequency (about 100 Hz). 

 

Can anybody help ?
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2 Replies
Altera_Forum
Honored Contributor I
76 Views

Ohh ... turns out that I got too hasty in putting up the above post. Its my mistake. 

 

The silly thing was, that with my original oscilloscope X-axis setting put to (20 ms / div), the signal was still appearing 5 divisions periodic, but jittery -which led me into believing that something was wrong. 

 

But just after I posted the above message, I checked correcting the X-axis setting to (10 ns / div) and now the signal turned out to periodic again with 5 divisions ( = 10*5 = 50ns => 20 Mhz), and this time .. stable as well

 

Couldn't find any option to delete my previous post, hence this apology. Sorry ! 

 

(perhaps the admin can delete this thread to avoid further confusions)
Altera_Forum
Honored Contributor I
76 Views

you are not the first one, and woun't be the last with such a mistake. 

and we all learn from mistakes, if we read and understand. 

so lets keep your posting for others to learn :-)
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