Can't implement HSMC on CycV Soc Dev Board

[AWann1]

Hello,

I'm using the supplied project and golden_top .v files for the Cyclone V SoC board. I'm just writing out a memory file through the HSMC bus, using the already defined pins.

However, I get this error for the LSB bit on the HSMC data bus:

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 I/O pad(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error (175020): The Fitter cannot place logic I/O pad in region (7, 81) to (40, 81), to which it is constrained, because there are no valid locations in the region for logic of this type.

Info (14596): Information about the failing component(s):

Info (175028): The I/O pad name(s): hsma_tx_d_p[0](n)

Error (16234): No legal location could be found out of 2 considered location(s). Reasons why each location could not be used are summarized below:

Info (175015): The I/O pad hsma_tx_d_p[0] is constrained to the location PIN_E8 due to: User Location Constraints (PIN_E8)

Info (14709): The constrained I/O pad is contained within a pin, which contains this I/O pad

Error (175003): The I/O pad location is occupied (2 locations affected)

Info (175029): PIN_E8. Already placed at this location: I/O pad hsma_tx_d_p[0]

Info (175015): The I/O pad hsma_tx_d_p[0] is constrained to the location PIN_E8 due to: User Location Constraints (PIN_E8)

Info (175029): PIN_D7. Already placed at this location: I/O pad hsma_tx_d_n[0]

Info (175015): The I/O pad hsma_tx_d_n[0] is constrained to the location PIN_D7 due to: User Location Constraints (PIN_D7)

If I don't define the hsma_tx_d bus as LVDS, then I do not get the errors. But, obviously I need to.

Has anyone had this occur with this dev board before?

[AWann1]

I did a little testing, if I remove that hsma_tx_d_p[0] line from the bus completely, the error just changes to the next signal in the bus. It says hsma_tx_d_p[1] can't be placed.

If I remove that one, it changes to hsma_tx_d_p[2], and so on until the last signal

[AWann1]

Ah, I found my problem. I had instantiated the negative side of the bus manually in my IO declarations. When assigning a bus the LVDS standard, that is unnecessary, as Quartus handles that for you. Once I removed the negative side, my errors went away

[Rahul_S_Intel1]

Glad to know that problem is solved . Just for giving an debug steps, if you are encountering fitter error make the pin placement auto and see the quartus is passing , If it is passing, you can assume the design does not have issues