Hi all,I had posted this issue previously, but nobody replied. I even created a webcase, but I am not getting any response from Altera. Anyway, I am trying my luck again. I have a Nios dev kit, which contains a Cyclone-1 EP1C20F400C7 FPGA. I am able to program the EPCS4 device on the board using Active Serial mode. But I am not able to program the FPGA using the JTAG header. In JTAG mode, when I click "auto detect", I get the message "Unable to scan device chain. Can't scan JTAG chain". I checked the voltages to the JTAG header. It is fine. I observed the TCK clock on the oscilloscope. I am observing a high value for around 50ms on the TDO line. The clock is seen only during this period. This is the time when it tries to scan the JTAG chain. Can someone kindly reply to this mail. I am stuck up since many days. thanks in advance, rajesh
Does the FPGA work, does it load the configuration you put into the EPCS?If you scan the JTAG chain on the Max connector, does it work? Are you sure you are putting the JTAG connector in the right orientation? Could you check all the JTAG signals with the scope, including TDI and TMS?
Hi Daixiwen,Thank you for the response. 1. The FPGA works perfectly when I use the EPCS4 device for configuration. 2. The Max connector is also facing the same problem: Can't access JTAG chain. 3. I am sure of the JTAG connection. 4. When I press auto-detect, I am observing a clock on TCK for around 65ms. Only for this duration, the TMS line goes low, and the TDO line goes high. At other times, TMS is high and TDO is low. The TDI signal goes low for around 5ms immediately after the 65ms interval. TDI is high at all other times. Can you please see what may be the issue. regards, rajesh
I'm not a jtag expert but it seems to me that the jtag slave will stay idle if tms stays at 0. Maybe someone else with more experience on jtag can confirm/deny this.Can you test your JTAG cable with some other hardware?
--- Quote Start --- but it seems to me that the jtag slave will stay idle if tms stays at 0. --- Quote End --- Absolutely correct. Before a JTAG instruction can be shifted into the device, TMS and TCK are setting the TAP controller to an active state. TMS states of '0' and '1' will be observed during the first clocks. Otherwise a hardware defect of the USB Blaster or your FPGA board must be expected. The TMS pin is used to drive NCONFIG in AS mode, so AS configuration would be still possible.
Hello FvM & Daixiwen,Thank you for the response. The byte blaster is not working on another board as well. This board contains a CPLD in JTAG mode. I was thinking that if AS programming is going through fine, then there should not be any problem with JTAG programming as well. I will try to change the blaster cable and then update the results. regards, rajesh