Can't set LoanIO by FPGA ,cycloneVsoc Dev kit

[CAlex]

Hi,

There is a IDC 2*7 on the board, the pins are HPS pins,here is the schematic

Most of them are connnected to the HPS Bank7. 

In HPS settings, I set the GPIO 58,59,60 as loanIOs(5,7 & 6 of the J32).

I set the IOs as output of the FPGA, and want to control them in my top layer

HPS setting

Top layer setting

Quartus setting

physical connnection(locations are checked correct)

Result of the pin, should be test_pulse,which is 0.

but no matter how I set them, they can't respond.

The boot method is baremetal SPL boot, I dont know whether it will influence the useage.

Reguards

Alex

[CAlex]

Update:

If you are using the same dev kit and facing the same problem as I do,

please check the following setting: HPS sysmgr reg on LOANIO and GENERALIO settings.

If the J31 jumper is shorted.(So that my pins above can be connected to the HPS board).

With the old problem solved, a new problem occurred.

I set the LOANIO 60 as output and assigned it as a clk output(320KHz), yet through Oscilloscope I got a analog signal, which shocked me.

I changed the duty and the output changed with that, so the code has no problem.

But what I want is the digital signal.

[aikeu]

Hi CAlex,

May I know if using the same pin as normal GPIO and is triggered by HPS, does it shows a normal digital signal?

Can try to loan with other pin as well to see if the same problem occured.

Thanks.

Regards,

Aik Eu

[CAlex · Accepted solution]

Hi,

thanks for the reply , problem is solved, I sent the 313MHZ signal instead of 313KHZ, the GPIO pin with 3.3 LVTTL std dont have such high bandwidth.

When I set to 313KHZ the result is good.

Reguards

Alex

[aikeu]

Hi CAlex,

Thanks for your sharing the root cause of your issue. It was helpful as I never thought of that as a cause for signal related issue.

I will close the thread for now.

Thanks again.

Regards,

Aik Eu