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Altera_Forum
Honored Contributor I
807 Views

Can't use 2 pins together on a single IDC connector (Altera DE1 Development Kit)

Hi. 

 

I have a problem with using 2 pins together on a single IDC connector. I don't have signal on each of 2 pins of single IDC connector. 

If I use only 1 pin on a single IDC connector, I can see correct signal on oscilloscope. 

 

If I use 1 pin on IDC_1 and 2 pins on IDC_2 as consequence I can watch signal on IDC_1 (where I use 1 pin), but I see nothing on IDC_2 

(where I use 2 pins) 

 

I use "fresh" Quartus II 13.0 Web Edition and Altera DE1 Development Kit (with Altera Cyclone II). But this problem takes place on 

my other "hand made" device (with Altera Cyclone III). 

 

You can see all cases (A,B,C,D) on the screenshot from attachments. 

 

(cases_A,B,C,D.jpg) 

 

You can see Quartus Archive Files (QAR) for every case (A,B,C,D) from attachments. 

 

(cases_from_screenshot.zip) 

 

PS. Same problems takes place, if I use "ALTPLL Megafunction" instead of my "Verilog Frequency Divider module". 

 

Thanks in advance.
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2 Replies
Altera_Forum
Honored Contributor I
42 Views

If I try to compile case C, on Quartus 12sp1, I get some warnings: 

 

 

--- Quote Start ---  

Warning (275080): Converted elements in bus name "GPIO_1" using legacy naming rules. Make any assignments on the new names, not on the original names 

Warning (275081): Converted element name(s) from "GPIO_1[1]" to "GPIO_11" 

Warning (275081): Converted element name(s) from "GPIO_1[3]" to "GPIO_13" 

 

Critical Warning (169085): No exact pin location assignment(s) for 2 pins of 4 total pins 

Info (169086): Pin GPIO_11 not assigned to an exact location on the device 

Info (169086): Pin GPIO_13 not assigned to an exact location on the device 

--- Quote End ---  

 

 

I don't use the schematic editor, so I'm not exactly sure what's going on, but it looks like Quartus is renaming GPIO_1[11] as GPIO_11, and the later name does not have a pin assignment. 

 

My advice: stop using the schematic editor.
Altera_Forum
Honored Contributor I
42 Views

2 rbugalho: Thank you for you help. 

 

I solved this problem. 

 

This problem associate with naming rules in Quartus II for cases with schematic. 

 

Information from Quartus 13.0 Help: 

 

 

--- Quote Start ---  

CAUSE: 

 

You created a Graphic Design File (GDF) or Block Design File (BDF) with the Max+Plus II software or with an older version of the Quartus II software. The Max+Plus II software had limited support for bus names in schematics and would sometimes rename the elements in the bus to work around these limitations. For example, it would rename bus names such as a[1..0], b[1], and b[0] to a1, a0, b1, and b0 respectively. The Quartus II software initially kept this behavior for backwards compatibility, but now supports a mode that preserves the natural bus names (with brackets) in your design. However, to avoid changing the behavior of the software for existing designs, the Quartus II continues to use the older naming conventions for legacy BDF and GDF design files. For new schematics, the Quartus II software preserves the original names in the design during compilation. 

 

In this case, the Quartus II software renamed the elements in the specified bus. Refer to the sub-messages for the names you should use when making assignments. If you make assignments on the original names, they will be ignored. For more information on schematic naming rules, refer to BDF Naming Rules. 

 

ACTION: 

 

If you want to preserve your bus names, set the Block Design Naming logic option to Quartus II. If you have existing assignments to the modified names and do not wish to change your working design, set the Block Design Naming logic option to Max+Plus II to eliminate this warning without changing the behavior.  

 

You can also update your BDF file to use Quartus II naming rules by clicking Save As, then choosing Block Diagram/Schematic File using Quartus II naming rules (*.bdf), and then saving it. 

--- Quote End ---  

 

 

Way to solve this problem: 

 

 

--- Quote Start ---  

Go to Assignments -> Settings -> Analysis and Synthesis Settings -> More Settings 

 

Go to Block Design Naming and change value from "Auto" to "Quartus II" 

--- Quote End ---  

 

 

Instance Naming Rules for Pin Names in the Block Editor 

 

 

--- Quote Start ---  

quartus ii software version 7.1 and earlier naming scheme: 

 

When a bus is split, it is converted into a group of pins, and each pin has a unique name. The name of each pin is the base name of the bus, with the index of the pin appended after the base name. 

 

If a bus a[0..3] is split, 4 pins are created: a0, a1, a2, and a3 

 

Note: Use a0 to refer to the first bit of the bus. 

 

quartus ii software version 7.2 and later naming scheme: 

 

When a bus is split, it is converted into a group of pins, and each pin has a unique name. The name of each pin is the base name of the bus, followed by a pair of square brackets, with the index of the pin between the brackets. 

 

If a bus a[0..3] is split, 4 pins are created: a[0], a[1], a[2], and a[3] 

 

Note: Use a[0] to refer to the first bit of the bus. 

--- Quote End ---  

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