Can you provide more detail of the SEU vulnerabilities for the Cyclone 10 GX?

[JDIAZ28]

Your Single Events Upsets page mentions that SEUs do not include latch-up in intel FPGAs. Has the Cyclone 10 GX (20nm process technology) been tested for SEL? What test conditions were used to test the component, bias, temperature?

Can more detail be provided as to how the MTBFI is calculated for the Cyclone 10 GX FPGA? How the FPGA was tested for it?

The MLAB in the Cyclone 10 GX FPGA does not have any mitigation. What is the SEU, MBU, SEFI cross section for this memory. What would be the impact in the FPGA operation if an upset in the MLAB memory occurs?

Cyclone 10 GX documentation mentions layout optimization for error detection and correction. Have these layout optimizations successfully mitigate MBU in the FPGA Memories. Has the mitigation been verified by test?

[JohnT_Intel]

Hi,

The SEU is tested on the CRAM bit and it is tested across supported temperature and speed grade.

Please refer to Cyclone 10 GX SEU Mitigation (https://www.intel.com/content/www/us/en/programmable/documentation/vua1487061384661.html#sam1403483263288) on the FIT calculation. The FPGA was tested with using external particle to attack the FPGA CRAM bit to see how easy it is flip and impact the functionality of the design.

There is no way to check the MLAB memory issue unless you create your own ECC to make sure that the SEU is not happening.

The mitigation is only targeting for CRAM bit and functionality. For the FPGA memories, we recommend user to use ECC to handle the RAM corruption

[JDIAZ28]

Thanks for the information. Any results that you can share regarding single event latchups on the 10 GX devices? Have SEL test been performed at worst case input voltage and temperature?

[JohnT_Intel]

I am sorry to tell you that we do not performed any SEL.