Cannot configure Cyclone 10 GX Kit via FPP.

[LChau1]

Hello,

I am currently trying to do a proof of concept on the Cyclone 10 GX Kit, using the kit collateral as a starting point. If anyone can see what I have missed this would be a huge help. I am generally following the FPP hands-on configuration guide on the fpgawiki, but it has not been updated with the Cyclone 10 GX. Here is what I have done so far:

1. MSEL to FPP (S1.1 & S1.2 => ON)
2. Created a basic blink project, am able to program the Cyclone 10 via JTAG and see my LEDs blink (using Golden Top)
3. Configured blink project to work in passive parallel x16 & compiled. Set unused pins to tri-state.
4. Converted my SOF to POF with CFI 2GB, set starting address to 0x0 on Page 0. Unsure what to do with option bits so made it a large offset address 0x8000000.
5. Programmed CFI using JTAG using a lower JTAG frequency (6MHz).
6. Restart board, no configuration.

With this process I have a couple questions.

1. I could not find a CFI flash memory map in the C10GX user guide. Is this still required? I believe I have already erased over my flash and option bits if this were the case.
2. Does the board CFG Max 10 come with a default image? It seems I am able to both program and recognize the CFI using JTAG. I was under the impression "System Max 10" in the kit collateral actually meant "Config Max 10" as per the user guide.

[ShafiqY_Intel]

Hi LChau1,

You may refer to the attachment file for FPP configuration mode guideline. This guideline is using Cyclone V GX development kit.

Cyclone 10 GX Dev Kit using CFI 1GB - MT28EW01GABA1LPC. (not CFI 2GB)

Hope this will help.

Thanks.😉

[MamaSaru]

I have the same problem as LChau1.

This development board has two MAX 10 devices, one called System and PFL for another.

The PFL MAX 10 can programmed through J11 dedicated JTAG header.

I try to reprogram the PFL MAX 10, but I can not find the programming Image for it.

I see cyclone-10-gx-kit-collateral folder contains only System MAX 10.

But looking into System MAX 10 design, I see P2 instance of PFL...

I am very confusing.

Please Help

[MamaSaru]

I have solved by myself.

I would share my study.

1. Select Passive Parallel x16 for compilation.

2. Select CFI_2Gb for flash size on convert programming file.

 We should enter the total size.

3. Option bit should locate on 0x30000 for convert programming file

 this information comes from system_max10 design. The folder name

 system_max10 is not proper indeed!

 It should be configuration_max10 like that.

Hello Intel FPGA, please revise the development kit doccumentation including this info.

[LChau1]

Thanks MamaSaru! That did it. Thanks so much.