FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
5930 Discussions

Capacitor sense button on MAX V CPLD Dev Board

Altera_Forum
Honored Contributor II
‎01-10-2014 08:11 PM
1,067 Views

Does any one know how is connected the capacitor sense button on the Altera MAX V CPLD Development Board? 

 

Ex.: Push buttons PB0 and PB1 are well documented in the "MAX V CPLD Development Board Reference Manual" where it is said that PB0 drives the M9 pin and PB1 drives the R3 pin. 

 

But noting is said about the capacitor sense button. I can't find the information no where. Neither can I find any schematic of the board. Very frustating! 

 

Can anyone help?
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎01-13-2014 09:01 AM
243 Views

The schematic is included with the board design files. The "capacitor sense button" seems to connect to Pin C11 without any additional electronic. 

 

P.S.: There are also design examples supporting the "touch" button.
0 Kudos
Copy link
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.