Changing h2f_user0_clk in Platform Designer (Quartus 18.0 Pro)

[FVanE1]

I have an Arria 10 with HPS on board. When changing the clock frequency of the h2f_user0_clk in Platform Designer from 100 MHz to 125 MHz, nothing happens. Measuring the clock shows me that it is still 100 MHz. I read in the documentation that this is a software managed clock. Do I have to rebuild the bootloader when changing the frequency of a software managed clock? What is the normal procedure and are the requirede steps to change a the frequency of the h2f_user0_clk ?

Best regards,

Frank

[EBERLAZARE_I_Intel]

Hi Frank,

Based on my experience, any changes made on the or with the HPS in Platform Designer, you are required to recompile the bootloader, .dtb file, preloader img etc.

Have you tried rebuilding everything and to see the changes made from Platform Designer?

Regards.

[FVanE1]

Hi,

I tried a recompile of all software stuff without success. How can I check if changes in clock frequencies in HPS are reflected in my software environment? Which file(s) are changed as result of a clock frequency change in HPS?

Best regards,

Frank

[EBERLAZARE_I_Intel]

Hi,

After the compilation for Arria 10 SoC in quartus, there is a folder called hps_isw_handoff, you can open the hps.xml using text editor and check the hps clk user0 and user 1 value, which is 400000000 in the default GHRD.