Channels mix-up with DE10-Nano ADC IP (the IP from Quartus IP Catalog for hardware only design, not the one from Platform Designer IP Catalog with Avalon-MM interface)

[JDali1]

Trying to use University Program IP from Quartus IP Catalog to interface ADC on a DE10-Nano board (altera_up_avalon_adv_mega), I found that channels are not routed correctly from connector to IP outputs.

My experiment: follow tutorial of section 3.3 of this document:

ftp://ftp.intel.com/pub/fpgaup/pub/Intel_Material/17.0/Tutorials/Using_DE_Series_ADC.pdf

IP Variation generated for 20MHz and 8 channels.

Result:

ADC_IN0 is routed to LED when SW is equal to 0 

ADC_IN1 is routed to LED when SW is equal to 2

ADC_IN2 is routed to LED when SW is equal to 3

ADC_IN3 is routed to LED when SW is equal to 4

ADC_IN4 is routed to LED when SW is equal to 5

ADC_IN5 is routed to LED when SW is equal to 6

ADC_IN6 is never routed to LED whatever SW value

ADC_IN7 is routed to LED when SW is equal to 7

Does anyone face same issue?

Other tests I made (Terasic ADC demonstration and other) seems to confirm the issue is located in this IP (altera_up_avalon_adv_mega).

[AnandRaj_S_Intel]

Hi Jean,

Can you check again using RTL viewer? It looks fine.

All ADC_IN channels are rooted correctly using mux.

There is no mix up in SW/select line or data/ ADC_IN.

Regards

Anand

[JDali1]

Hello Anand,

Thanks for you answer.

I generated a new IP variation with default parameters (ADC clock = 12.5MHz / 8 channels / system clock = 50Mhz) and repeated the test. This time everything is fine, no mix-up, so maybe there is some timing issue at max speed on the DE10-Nano.

As I would need to use ADC at max frequency for my project, I will repeat the test to find max possible frequency without issue. In the mean time any advise is welcome!

Regards,

Jean-Guilhem