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flying probe test detected the impedance to GND on net "P1v1_FPGA" lower than normal value.
NG value is 42 ohms.
Normal value is 190 ohms.
2 pcs D/C2049 were found issue at our NPI project need FA.
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Hello FTang,
Thank you for posting in Intel Ethernet Communities.
Can you please provide the exact model of the product that you are requesting for an assistance? In case that this is FPGA product, we may need to move this thread to the appropriate topic to further assist you.
Looking forward to your reply.
We will follow up after 3 business days in case we don't hear from you.
Best regards,
Crisselle C.
Intel® Customer Support
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Hello FTang,
Thank you so much for the quick response. However, we still cannot find model that you provided.
By the way, can you also confirm if you are designing a board or a system with embedded network controller?
How are you trying to implement Breton in the system?
If you have questions, please let us know. In case we do not hear from you, we will make a follow up after 3 workings days. Thank you.
Best regards,
Michael L.
Intel® Customer Support Technician
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Hello Michael,
Maybe I misunderstood about the model. The Intel product model of 5CSTFD55F3117NF is Cyclone V E. It is a FPGA.
Cisco design a system with embedded network controller. For the issue we encountered, it is just impedance between pin "P1v1_FPGA" to GND is lower than normal.
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Hello FTang,
Can you help to provide the pin name involved?
Wani
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Hi Wani,
The pin name involved are VCC1-26 and VCC_HPS1-13.
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Hello FTang,
Thank you for the prompt response.
Since your query involves FPGA, please be informed that this will be best answered by our FPGA Support team. We will help you to move this post to the designated team for further assistance. Please feel free to contact us if you need assistance from Ethernet support team.
May you have an amazing fay ahead!
Best regards,
Crisselle C.
Intel® Customer Support
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Hi Fairy,
VCC1-26
VCC_HPS1-13
Vcc to GND lower than usual issue is highly suspected caused by an EOS event. This may be caused during reflow or just by someone touching the device or board without discharging themselves.
In order to avoid electrical damage, the device should always be handled in a static-free environment and all the input signals should remain within specified limits, as recommended in the PSG Data Book and associated application notes, at all times.
For your information, EOS is fall under mishandling issue.
Wani
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