Hi,I'm trying to design an 640x480 VGA controller for which the simulation seems alright. However, when I program the CYCLONE || FPGA STARTER KIT, nothing appears on the screen. I suspect that there's no clock (25.175MHz) driving the controller's clock input. Using the following procedure : assignment tab -> classic timing analyser settings -> individual clocks, I'm trying to get a clock to drive the controller'd clock input by tying the clock_in entity clock input (clock_in) to the clock_27 or clock_50 onboard clocks. Once this done, I've chosen 25.175MHZ as the highest frequency from the default required fmax on the Classic Timing Analyser Setting. I'd like to use the onboard clocks for my projects, but unless something is wrong with the code, I'm not doing the right thing to get the clock. Any idea on what I'm doing wrong? Regards,
Hi,I think that you are correct in saying that I suspect that there's no clock (25.175MHz) driving the controller's clock input.......... : This is because there is no 25.175MHz crystal oscillator on the board. You have three ways of generating your required clock. 1) An external piece of circuitry can provide a 25.175MHz clock into the development board through the external clock, EXT CLOCK, input. However since you want to use the onboard clocks this solution will not be suitable for you. 2) You can instantiate a PLL and drive it with the 50MHZ clock and attempt to generate the 25.175MHz clock from that. You can then use this to drive your graphics core. 3) You can change the timing of your graphics core so that it can be driven directly from the 25MHz clock. To do this you need to calculate how many clock cycles are need to complete the back porch, front porch, border etc during the horizontal and vertical scan periods at the new frequency and adjust your graphics core accordingly. ASSIGNMENT tab -> Classic Timing Analyser Settings -> INDIVIDUAL CLOCKS, I'm trying to get a clock to drive the controller'd clock input by tying the clock_in entity clock input (clock_in) to the ClOCK_27 or CLOCK_50 onboard clocks. Once this done, I've chosen 25.175MHZ as the highest frequency from the Default required fmax on the Classic Timing Analyser Setting. By doing this you achieve nothing! It will ensure that you have met the timing constraints but I do not think that it will generate a 2.175MHz clock for you unless I have misunderstood what you are doing. Ben
Thanks Ben for answering.The CYCLONE || Starter Kit has on board 3 crystals, 24MHz, 27MHz, and 50MHz. Using VHDL code, I know how to use the 7_SEGMENTS, KEYS, LEDS, etc..., but I'm having problems to use one of the crystal oscillators listed above using the same technics used to access the other peripheral onboards. For example, if I want to write the key values to the LEDs, using the code below will do : entity key_To_Led is port( key : in std_logic_vector(9 downto 0); -- key and ledr are the symbolic -- names for the ledr : out std_logic_vector(9 downto 0); -- 9 keys and 9 red leds on my -- kit. end key_To_Led; architecture behavior of key_To_Led is begin ledr <= key_To_Led; end behavior; Now, if if for example I want to access the 50 Mhz onboard clock generator, I would have probably to use the same type of coding as : entity vga_ctrl is port( CLOCK_50 : out std_logic; -- Symbolic name for 50Mhz onboard 50 Mhz -- clock clock_in : inout std_logic; -- VGA controller clock input; ); end vga_ctrl; architecture behavior of vga_ctrl is begin clock_in <= CLOCK_50; -- Logically, this should work; but still, it -- does'nt. end behavior; Again, unless there's something wrong with my code in general, I do not know what else to do to access any of the onboard clock generators. I'll appreciate any idea that would help. Regards,
hiAre you sure the code below doesnt have a problemm!! I am not suree about the real problem you are facing.. just a look at your code made me to comment... entity vga_ctrl is port( CLOCK_50 : out std_logic; -- Symbolic name for 50Mhz onboard 50 Mhz -- clock clock_in : inout std_logic; -- VGA controller clock input; ); end vga_ctrl; architecture behavior of vga_ctrl is begin clock_in <= CLOCK_50; -- Logically, this should work; but still, it -- does'nt. end behavior; You have declared CLOCK_50 as OUT and you are tryingg to assign it to clock_in.........
Hi,Thanks for answering. No, I know it does not work. I just do not know how to connect an onboard crystal to the entity clock. Worse, I do not even have any idea on how to do that with the Cyclone 2 Starter kit. However, I've learned how to work with the other onboard units using VHDL like the four 7_Seg, the leds, the switches; but for the onboard clocks, I do not know how because I do not have an example on how to do that. I've tried many ways, but none worked. All I need, is someone that could give me a small code example on how to use the onboard crystal clocks using the entity and architecture I gave here. As for now, I'm stuck with a 2000 lines of code program that works perfect using simulation, but does not work when loaded into the FPGA because there's no clock friving the system because I do not know how to use the onboard clock that I need badly for a demonstration to be done next week for people coming from Corea and my boss is starting to regret using the Cyclone 2 board that I personnaly like; but the people from corea won't care less and we will lose the contract if I can't do nothing until then. All I need, is a single line of example and I'm done.. Good luck for me!!! Regards,
Hi,Because of lack of time, I've finally used the 27 Mhz onboard clock for the project. The clock was not too critical anyway and the whole thing works as expected. Thanks for the reply. Regards,
Also i am using 27Mhz for my VGA controller for 640x480 (@60Hz) video and it works. But i couldn't find the reason. How does it work ? all the timings are wrong when we use 27MHz instead of 25.17 MHz. Do you know how is it possible?