Clock Pins for Arria 10 SoC Development Kit

[GSagl1]

Hello,

I am looking at the pinout pdf file for the Arria 10 SoC Development Kit, and so far it just looks like an alien language.

I am just looking for a pin that I can use in my FPGA Verilog design that has more than 135 MHz.

I am using the kit with the fmcdaq2 board and in the example project there is 333.333MHz clock (tx_ref_clk) that is connected to PIN_N29 (and there is also "tx_ref_clk(n)" connected to PIN_N28 for some reason), but even though I use this clock, my design doesn't work properly. I believe this clock signal changes and is not actually continuously 333.333MHz, so that is why it is not working. Is there any pin that I can use in my design that has a clock of at least 135 Mhz? (I can use Altera IOPLL IP to choose my desired clock, so I would appreciate it if the frequency is much higher)

[sstrell]

What you reference is a differential clock on those 2 clock pins, so that might not be what you want.

I'm presuming it's this kit but the pin numbers you mention don't match up with your description of them according to the documentation: https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/arria-10-soc-development-kit.html

Is that the kit you're using?

[GSagl1]

Yes, this is what I am using. Perhaps the pin I am referring to is connecting to the fmcdaq2 board I have, and it is providing that signal.

I have been looking at the pinout file and the user guide of this development kit however the user guide isn't exactly as clear as it could have been, and the pinout is some sort of an alien language. Can you help me out and give me some pin that actually has at least 135 MHz frequency? It's fine if it's 300, 500, 750MHz or whatever, as long as it s more than 135MHz.

[EngWei_O_Intel]

Hi there

If you check on "The Clock Control" section in https://www.intel.com/content/www/us/en/programmable/documentation/iga1434736665480.html#iga1439246083721, you are able to set the freq through the apps.

You can check on the schematic for the connection of Si5338 to the FPGA here:

https://www.intel.com/content/dam/altera-www/global/en_US/support/boards-kits/arria10/soc/Production_files/a10_soc_devkit_03_31_2016.pdf

Thanks.

Eng Wei

[GSagl1]

Yes, except those apps do not work with Quartus 17.1. They apparently work with 15 something.

[EngWei_O_Intel]

Hi there

I am not sure if there is any library differences from version 15.1 to 17.1. So, are you able to work with it on 15.1, which according to the readme file, this is the Quartus version where the ref design is built up with.

Thanks.

Eng Wei

[GSagl1]

I actually have Quartus 17.1 on my setup. And I have tried with 17.1 but there were some errors that popped up on screen even though I did exactly as it was said in the guide. I might have to try with 15.1, however, other things might break. And also on this forum there were some posts saying it had to be 15.1, so I think it really does not work with other versions. Aren't there any other clock pins?

[EngWei_O_Intel]

Hi there

I am sorry for overlooking on this. This seems to be Software related issue. I suggest you to file another request on this specific Software issue, so that Software related expert would be able to assist you on this. I am covering more into IO and PLL related issue.

Thanks.

Eng Wei 

[GSagl1]

Hello,

I have downloaded Quartus Prime Standard 15.1.0 and tried to make BTS work, didn't work. I updated it to 15.1.2.193, didn't work. I downloaded just the Quartus Programmer 15.1.0 and still it does not work. I can't see any way to update just the Quartus Programmer to 15.1.2.193.

I have tried to start BTS with Administrator, no luck, I have tried to upload the bts_config.sof to the FPGA then tried it, didn't work.

I have opened a command window with Admin privileges and types "java -jar bts.jar -verbose" to have verbose output. I have this window popping up (I have changed the switches as required, sw1="on off off off" and the other one with sw3) and below is the verbose output. Could you have a look and tell me if I am doing anything wrong?

----output----

java -jar bts.jar -verbose
verbose mode on
Success!
Current OS:Windows 10
Sep 03, 2021 9:15:21 PM com.altera.bts.BtsView <init>
INFO: Board version: Rev B, chip version: ES2
Sep 03, 2021 9:15:21 PM com.altera.bts.systemconsole.client.ClientApp attachServer
INFO: [C:\altera\15.1\qprogrammer/sopc_builder/bin/system-console, --server]
Sep 03, 2021 9:15:21 PM com.altera.bts.systemconsole.client.ClientApp attachServer
INFO: Here is the standard output of the command:

Sep 03, 2021 9:15:25 PM com.altera.bts.systemconsole.client.ClientApp attachServer
INFO: TCP PORT: 50443
Sep 03, 2021 9:15:33 PM com.altera.bts.systemconsole.client.JtagInfo retrieveDeviceList
INFO: 5 device detected: /devices/10AS066H(2ES|3ES|4ES)|..@1#USB-1 /devices/10AS066H(2ES|3ES|4ES)|..@1#USB-2 /devices/5M2210Z|EPM2210@3#USB-1 /devices/5M2210Z|EPM2210@3#USB-2 /devices/5M2210Z|EPM2210@4#USB-2
Sep 03, 2021 9:15:33 PM com.altera.bts.systemconsole.client.ClientApp getCompatibleBoardInfoArray
INFO: System Max matched: true, Fpga matched: true
Sep 03, 2021 9:15:33 PM com.altera.bts.systemconsole.client.ClientApp getCompatibleBoardInfoArray
INFO: System Max matched: true, Fpga matched: true
Sep 03, 2021 9:15:36 PM com.altera.bts.BtsView <init>
INFO: Selected JTAG cable is: USB-BlasterII on localhost (USB-2)
Sep 03, 2021 9:15:36 PM com.altera.bts.BtsView <init>
INFO: FPGA device on index 1, System MAX on index 3
Sep 03, 2021 9:15:36 PM com.altera.bts.InstanceChecker registerInstance
INFO: Application Register. Type: Board Test System GUI
Sep 03, 2021 9:15:36 PM com.altera.bts.systemconsole.client.SysConService <init>
SEVERE: java.io.IOException: Get master service paths failed! Device: "/devices/5M2210Z|EPM2210@3#USB-2" Type:
Sep 03, 2021 9:15:36 PM com.altera.bts.InstanceChecker registerInstance
SEVERE: java.io.IOException: Claim master service failed! Type: Path: mem_0

----output end----

[GSagl1]

Hello,

Do you have some time to look into it? I still cannot make it work, I've been working on it constantly.