Clock generator on DE0-Nano-SoC

[Altera_Forum]

The Terasic DE0-Nano-SoC contains a programmable clock generator (CDCE937) which is controllable from I2C. The bundled example GHRD design has conditional FPGA port definitions (CLK_I2C_SDA/SCL), but does not assign any pins to them. When I investigate the schematics, it seems the I2C bus is not connected to the FPGA at all. So it seems that Terasic planned to connect them to the FPGA, but haven't?

[Altera_Forum]

The clock generator is part of the "system" so it has not been placed on the board to be used by the end user. This chip generates all the clocks needed for the FPGA, ARM core and other parts of the system, which require low jitter clock signals. You cannot reprogram it unless you hack into the I2C lines with something like bus pirate and changes its configuration. If the I2C lines are not connected to anything, by guess would be Terasic probably have this chip pre-programmed.

[GAnic]

Actually the pins are connected and you can reprogram the CDCE937 chip through I2C from the FPGA, the existing configuration uses only the PLL1 and PLL2 to create all frequencies so you can program the PLL3 to get an arbitrary frequency on the FPGA_CLK2 pin for example. The connections to the FPGA are SDA=AA4 and SCL=U10, the address of the chip is the default (as noted in the schematics)

The default configuration (registers 0x00-0x3f) is as follows:

A1 01 34 01 02 50 80 00 00 00 00 00 00 00 00 00 00 00 00 00 4D 02 08 00 FE BA 32 07 00 40 02 08 00 00 00 00 0D 02 04 00 FE BA 32 07 00 40 02 08 00 00 00 00 8D 02 00 00 6A 4A A3 4C 00 40 02 08