FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5276 Discussions

Clock sharing between the Arria 10 Transceiver Banks

PShetty
Novice
1,123 Views

Hi,

We have Arria 10 SoC design,where we are using 4 high speed transceiver channels from each bank(1E,1F,1C,1D) . 4 Transceiver PHY IPs are used to configure the 4 channels from each banks. My question is can I use single ref clock for all these 16 channels, if so what are the rules and procedure to follow?

 

Thank you.

0 Kudos
4 Replies
CheePin_C_Intel
Employee
191 Views

Hi,

 

Sorry for the delay. ​If I understand it correctly, the 4 XCVR banks that you are referring to are on the same side of the device. For your information, you can use one refclk to drive all the XCVR channels on the same side of device. You may try to create  a simple test design and run through Fitter to further verify.

 

Thank you.

PShetty
Novice
191 Views

Hi cpchan,

Thanks for the reply. Yes, 4 XCVR banks are on the same side of the device. I do have 4 different Qsys design for 4 xcvr operation. currently I am providing reference clock for each from its respective bank. Is there any rules i have to follow to use single REF clock to drive all 16 channels?

 

Thank you.

CheePin_C_Intel
Employee
191 Views
Hi, I am not aware of any specific restriction on this. However, it is recommended for you to run through Fitter compilation, and then check if there is any warning related to the refclk placement or driving distance. Thank you. Best regards, Chee Pin
PShetty
Novice
191 Views

Hi,

Thank you so mcuh. I will create a test design and verify.

Reply