I am using DE2-115 development board. I have written a verilog code where I am trying to generate a sequence of 1' and 0's using the clock frequency of 50MHz and I am getting the output as shown in the attached figure 1 below. The output should be a square wave, but this does not looks like the case, Can anyone help me on that ?Whereas when I try to look at the signal obtained at lower frequency of 5MHz, obtained from the clock of 50 MHz, using the code to divide the clock frequency by 10 and it looks a lot like a square wave, as shown in attached figure, 20141024_143558.jpg (http://www.alteraforum.com/forum/attachment.php?attachmentid=9596&stc=1&d=1414625601). Also the third figure is the signal generated of frequency 25 MHz, using clock of 50Mhz and the code written just divides the frequency by 2 and is shown in figure 20141028_133959.jpg (http://www.alteraforum.com/forum/attachment.php?attachmentid=9597&stc=1&d=1414625620) Can anyone helo me on why I am getting these problems of different shapes of the signal for different frequencies. Regards Himanshu
There is no problem at all, your clock looks fine. Sharp edges are only in drawings in science books. In reality you have unmatched impedances between systems, all the electromagnetic effects, etc. And with increasing frequency these things are getting only worse, try scope on 100 or 200 MHz clocks.
I imagine it also has something to do with the speed of the IO transistors. I do not know what the slew rate of these transistors is, but someone else might know. Try looking at each clock on the same division settings. I think you will see each edge has about the same slope.