Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Valued Contributor III
2,907 Views

Communication PC-De0 Nano

Hello everyone, 

I need to make a GUI that could communicate between pc and my De0 nano. 

I could make the GUI with QT but I don't know how the communication work. 

I am aware that every time I connect my fpga to my pc, there is always a new com show up in the device manager. 

Based on my past experience using microcontroller, it is possible to use serial communication via usb and display the data using hyperterminal. 

What is my option to send a packet of data from fpga to pc? Could it perform bidirectional communication? 

Thank you everyone.
0 Kudos
33 Replies
Highlighted
Valued Contributor III
74 Views

 

--- Quote Start ---  

 

I need to make a GUI that could communicate between pc and my De0 nano. 

I could make the GUI with QT but I don't know how the communication work. 

 

--- Quote End ---  

The USB interface to the DE0-nano is a USB-Blaster. 

 

You can communicate from the host via a couple of mechanisms; 

 

1) SLD Virtual JTAG core, and quartus_stp Tcl procedures 

 

2) JTAG-to-Avalon-MM master and SystemConsole 

 

3) Direct access via FTDI drivers 

 

If you want to communicate via a QT GUI, then you could communicate with (1) and (2) via sockets. Unfortunately SystemConsole has broken fileevent, so servers there can not deal with multiple clients (you have to block on a client socket). Unfortunately Altera do not provide Avalon-MM access functions from quartus_stp, so you'd have to reverse engineer the protocol. (3) also requires reverse engineering the protocols. 

 

I think there is also the option of a JTAG-UART as well, and then communicating via nios2-terminal. However, since this is not a Virtual COM port, I think that solution would be a pain too. 

 

Option (1) is currently the best documented interface for custom communications via USB ... unfortunately, that is being generous (since the documentation has errors ...) 

 

If you are just starting out with FPGAs, then just go an buy an FTDI FT245BM module from Digikey for $20 and use that. The device appears as a Virtual COM port, and the interface logic is pretty easy to implement. 

 

Cheers, 

Dave
0 Kudos
Highlighted
Valued Contributor III
74 Views

Thank you so much Dave for your quick reply. 

 

"then just go an buy an FTDI FT245BM module" 

(3)Actually De0 nano has already FTDI FT245BL. Should I still buy the FTDI FT245BM module although De0nano has already FTDI chip on board? 

 

Dave, could you also give me a good link or pdf regarding (1) and (3)? 

I just don't know where to start.  

 

Thank you again, Dave. 

 

Gunardi
0 Kudos
Highlighted
Valued Contributor III
74 Views

 

--- Quote Start ---  

 

"then just go an buy an FTDI FT245BM module" 

Actually De0 nano has already FTDI FT245BL. Should I still buy the FTDI FT245BM module although De0nano has already FTDI chip on board? 

 

--- Quote End ---  

The USB-Blaster circuit is constructed using an FTDI FT245 plus a CPLD. The functionality of this circuit is not documented by Altera (but there are details on the web). I also see that Terasic has stopped publishing the circuit diagram in the schematic too, eg. there is nothing in the DE0-nano schematic.  

 

 

--- Quote Start ---  

 

could you also give me a good link or pdf regarding (1) and (3)? 

 

--- Quote End ---  

The SLD Virtual JTAG interface has a users guide: 

 

http://www.altera.com/literature/ug/ug_virtualjtag.pdf 

 

Everything else has to be reverse engineered using SignalTap II. I've been writing some tutorials on how to use these features. I'll try to finish them and post links. 

 

Cheers, 

Dave
0 Kudos
Highlighted
Valued Contributor III
74 Views

Thanks Dave for your quick response. 

I will try to read up the pdf immediately. 

If it is not too much to ask, when will the tutorials be finished? 

Thank you Dave.
0 Kudos
Highlighted
Valued Contributor III
74 Views

 

--- Quote Start ---  

 

If it is not too much to ask, when will the tutorials be finished? 

 

--- Quote End ---  

Whenever I get time :) 

 

Which one sounds the most interesting to you? 

 

Cheers, 

Dave
0 Kudos
Highlighted
Valued Contributor III
74 Views

Hello Dave, 

I prefer the solution that is onboard solution. I mean why should I buy a new device if there is a solution that already onboard. I think I prefer to use virtual jtag. 

As a matter of fact, I found 2 solutions: 

1. Buy a usb-ttl 3.3V and connect it to I/O port of De0Nano FPGA board. Of course using this solution I need to write a serial communication protocol. 

2. Use another microcontroller board and connect the uc and fpga I/O pin. The protocol between both of them could be serial or paralel protocol(depending on how much pin I would like to use or how much pin is available). At least use 2 wire, if using I2C. The fpga act as master and uc act as slave that transmit or receive data to pc. 

 

I find that both solutions is a waste of resource(my professor think so too especially solution no 2) because I think the De0 nano has to be able to transmit and receive data to pc someway. 

 

Thank you so much Dave. 

Wish you could finish it at once. :)
0 Kudos
Highlighted
Valued Contributor III
74 Views

 

--- Quote Start ---  

 

As a matter of fact, I found 2 solutions: 

1. Buy a usb-ttl 3.3V and connect it to I/O port of De0Nano FPGA board. Of course using this solution I need to write a serial communication protocol. 

2. Use another microcontroller board and connect the uc and fpga I/O pin. The protocol between both of them could be serial or paralel protocol(depending on how much pin I would like to use or how much pin is available). At least use 2 wire, if using I2C. The fpga act as master and uc act as slave that transmit or receive data to pc. 

 

I find that both solutions is a waste of resource(my professor think so too especially solution no 2) because I think the De0 nano has to be able to transmit and receive data to pc someway. 

 

--- Quote End ---  

These are all good solutions. I like that you took the time to think about it. 

 

 

--- Quote Start ---  

 

Wish you could finish it at once. :) 

--- Quote End ---  

I'll try to grant your wish. Ping me in a couple of days and see if I have something ready. 

 

Cheers, 

Dave
0 Kudos
Highlighted
Valued Contributor III
74 Views

Will do, Dave. :) 

Thank you.
0 Kudos
Highlighted
Valued Contributor III
74 Views

Hello Dave, 

I have finished the pdf that you gave but not quite get it.  

That's why I am trying to use Virtual Jtag starting with a simple verilog design which is a 4 bit counter. 

I'm starting by using megawizard manager. I don't quite understand at page 4 of virtual jtag megawizard. What is actually stimulus? I think this is where we define the shifting operation(not sure). How should we know how much delay needed for the stimulus? 

 

I also a bit confuse of the diagram block of virtual jtag that shows during megawizard. 

Why TDO and ir_out are put at the left side and tck, tdi, ir_in are located at the right side? I think it should be in contrary because TDI(Test data input), TCK(Test clock) and IR_in are the input of the VJI(virtual jtag). 

 

I think I am asking too much. Hehehe... :) Sorry. 

By the way, how about the progress of your tutorial? 

 

Thank you so much
0 Kudos
Highlighted
Valued Contributor III
74 Views

 

--- Quote Start ---  

 

I am trying to use Virtual Jtag starting with a simple verilog design which is a 4 bit counter. 

 

--- Quote End ---  

That's a good start. 

 

 

--- Quote Start ---  

 

I'm starting by using megawizard manager. I don't quite understand at page 4 of virtual jtag megawizard. What is actually stimulus? I think this is where we define the shifting operation(not sure). How should we know how much delay needed for the stimulus? 

 

--- Quote End ---  

The simulation feature of the component does not work, so don't bother to enter anything in that field. The documents I post will show how the component is broken. 

 

 

--- Quote Start ---  

 

I also a bit confuse of the diagram block of virtual jtag that shows during megawizard. 

Why TDO and ir_out are put at the left side and tck, tdi, ir_in are located at the right side? I think it should be in contrary because TDI(Test data input), TCK(Test clock) and IR_in are the input of the VJI(virtual jtag). 

 

--- Quote End ---  

tdi and ir_in are inputs to your design, but they are outputs of the virtual JTAG component. Similarly ir_out is an output from your design, but its an input to the virtual JTAG component. I know, the names are ambiguous :) 

 

 

--- Quote Start ---  

 

By the way, how about the progress of your tutorial? 

 

--- Quote End ---  

Not ready for release yet, but I did work on it over the weekend. 

 

Cheers, 

Dave
0 Kudos
Highlighted
Valued Contributor III
74 Views

Thank you, Dave. 

Don't worry. Thanks for your effort during weekend. :) 

I don't know how to show my gratitude
0 Kudos
Highlighted
Valued Contributor III
74 Views

How about TCK? Does it also the output of the virtual jtag(vji)? I think we should generate a clock which we feed into the vji(not sure either).

0 Kudos
Highlighted
Valued Contributor III
74 Views

 

--- Quote Start ---  

How about TCK? Does it also the output of the virtual jtag(vji)? I think we should generate a clock which we feed into the vji(not sure either). 

--- Quote End ---  

The Virtual JTAG component ports TCK/TMS/TDI are outputs, and the TDO signal is an input. These pins correspond to the signals coming from the FPGA pins via the Virtual JTAG component into your design. 

 

For your first design, you can ignore all of these signals, and just wire ir_in to your LEDs, and ir_out to some push buttons. You can then use quartus_stp and device_virtual_ir_shift to write to the LEDs and read from the push buttons. 

 

Cheers, 

Dave
0 Kudos
Highlighted
Valued Contributor III
74 Views

Hello Dave, 

I was just telling my proffesor that I would like to use virtual jtag instead of usb to Ttl(serial). 

Something about his background, he is not familiar with fpga but familiar about communication between pc and microcontroller. 

He said that I cannot just get my data on pc side from my fpga just like usb to ttl do with hyperterminal. He is not questioning about my programming on fpga side but he is questioning about my programming on pc. He said if I use the jtag, I should make my GUI(on pc side) to follow jtag protocol(which is complicated). 

He also said I could not get the data from hyperterminal directly (like usb to ttl do)even if my virtual jtag on fpga do work. 

I don't really get it. 

Could you please tell me what he think?  

All this time I think I could send my data from fpga to pc using virtual jtag via hyperterminal just like usb to ttl(serial) do. 

Thank you, Dave.
0 Kudos
Highlighted
Valued Contributor III
74 Views

 

--- Quote Start ---  

 

I don't really get it. 

Could you please tell me what he think?  

All this time I think I could send my data from fpga to pc using virtual jtag via hyperterminal just like usb to ttl(serial) do. 

 

--- Quote End ---  

What your professor is wisely telling you is that you should take the 'easiest' approach. If you use a standard serial port device on the PC-end to communicate with your FPGA, then the 'work' is at the FPGA end. However, you now have to have two pieces of hardware hanging off your PC USB ports (the FPGA board and the serial adapter) and then you have to wire the serial cable into the DE0-nano board. 

 

The JTAG interface provides a mixture of work at both ends. At the FPGA side, you have to write some logic to interface to the component. At the PC end, you have to use the Altera Tcl scripting interface. 

 

Using the Tcl scripting language, its fairly simple to create a server, i.e., a program that provides clients access to the FPGA hardware. 

 

The tutorial shows how to create an FPGA design, provides Tcl scripts that implement a server, and a client Tcl/Tk GUI for turning LEDs on or off. You can show your professor this interface, and he can then decide whether or not he likes it. 

 

Cheers, 

Dave
0 Kudos
Highlighted
Valued Contributor III
74 Views

Thank you, Dave. 

Is it possible to send data from fpga using virtual jtag and shows the data at hyperterminal or other similar program like qt comport? 

I still want to try it.
0 Kudos
Highlighted
Valued Contributor III
74 Views

 

--- Quote Start ---  

 

Is it possible to send data from fpga using virtual jtag and shows the data at hyperterminal or other similar program like qt comport? 

I still want to try it. 

--- Quote End ---  

It is not possible directly with the Altera component, since they do not provide an operating-system device driver. However, you can get the same effect using a server. For example, you can connect a terminal program to a socket and send characters over the socket. This is what the client/server application I have written does. The server side of the application takes the place of the device driver. 

 

Cheers, 

Dave
0 Kudos
Highlighted
Valued Contributor III
74 Views

Ok then, I am looking forward to your tutorial. 

I will try digging more about this issue.
0 Kudos
Highlighted
Valued Contributor III
74 Views

Hello Dave, have you finished the tutorial? 

I am really curious about virtual jtag. 

In my uni, everyone use usb to ttl or rs232 so it is nothing special. I'd like to try something else. 

Thank you Dave.
0 Kudos