FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
6189 Discussions

Configuration pins 10M02SCE144I7G

JRe2s
Beginner
‎11-19-2024 09:21 AM
193 Views

Hello Team,

 

could you review the attached schematics? In particular the config pins of the FPGA?

 

Best regards,

Jochen

Labels (1)
Preview file
392 KB
0 Kudos

Link Copied

5 Replies
FvM
Honored Contributor I
‎11-19-2024 01:24 PM
173 Views
Why are you connecting JTAGEN to JTAG connector pin 8?
0 Kudos
Copy link
JRe2s
Beginner
‎11-19-2024 09:29 PM
148 Views

Maybe this is wrong wired. Should the JTAGEN be pulled high or low if the pin is not used as an IO?

0 Kudos
Copy link
FvM
Honored Contributor I
‎11-19-2024 10:39 PM
140 Views
In response to JRe2s
JTAGEN should be pulled high by 10k to enable JTAG pins in user mode. Or configure JTAGEN in dual purpose pin setup as IO to enable JTAG pins unconditionally.
In response to JRe2s
0 Kudos
Copy link
JRe2s
Beginner
‎11-20-2024 12:49 AM
129 Views
In response to FvM

OK, thanks. The other config pins are wired correct?

In response to FvM
0 Kudos
Copy link
FvM
Honored Contributor I
‎11-20-2024 02:24 PM
96 Views
In response to JRe2s
Yes, think so.
In response to JRe2s
0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.