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Conflicting information regarding PCIe reference clock I/O standard (HCSL)

Honored Contributor II



I'm looking at conflicting information with regards to the electrical specification for the transceiver input reference clock for Arria II devices. 


Volume 2 of the Arria II Device Handbook (Transceivers) specifies a particular termination scheme (off-chip) for the HCSL standard (I've been using that I/O standard in the prototype design). So far I've been using the Arria II GX Development Kit for prototyping and just specified HCSL for the transceiver input reference clock which worked just fine (despite the fact that Quartus II software configured differential on-chip termination of 100 ohms erroneously as pointed out in an Altera knowledge base article). My understanding is that I might have gotten lucky so far as I don't see the specified termination scheme in the schematic and layout of the development kit. In fact, it doesn't seem to matter whether a differential termination of 100 ohms is enabled or disabled in my prototype design. It always works. 


Now, we've just designed our own PCIe board using the Arria II GX Development Kit as a "template". That is, just like on the development kit, we've connected the differential PCIe reference clock lines (100 MHz) straight from the edge fingers to the dedicated transceiver reference clock inputs. This seems to have been a mistake as I don't see a clock signal in the FPGA (I've created an example design where I could tap into the reference clock, driving a counter for blinking an LED - no transitions at all). I still think it should work as we're doing exactly the same thing as on the Arria II GX Development Kit and I can't image that the missing termination scheme in the development kit is a design mistake. So I guess I'm missing something here and would very much appreciate if anyone can point me into the right direction. 



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