Hi, I was checking reference designs about how are the connections for a DDR3 memory and its controller :
In the Controller's side:(just for example),the Address bus is connected in this way : A0 to A<0>, A1 to A<1>, ..., A15 to A<15> and Data bus is connected in this way : DQ<0> to RDQ0, DQ<1> to RDQ1,
In the Memory side :
The Address Bus is connected A0 to A<0>, A1 to A<1>, there is no difference , but the Data Bus have connected net with different number names that in the controller's side, for example : The DATA0 of the memory is connected to the net DQ2, and DATA1 of the memory is connected to the net DQ5, and it's the same thing with the other pins of Data Bus (in the Memory side)
bellow Screenshot from schematic (file DDR3_UDIMM_RC_E_REV09_20070912_SCH.pdf from
www.jedec.org)
https://www.alteraforum.com/forum/attachment.php?attachmentid=7816 I've checked in design on DDR2 but , it's not happen with DDR2, or It happen?, I hope can explain me , because I'm quite confused
I Attach the file DDR3_UDIMM_RC_E_REV09_20070912_SCH.pdf
