Community
cancel
Showing results for 
Search instead for 
Did you mean: 
APaci1
Novice
760 Views

Connecting 2 TSE (with micrel PHY) each other: Link down

i! I have my Arria10 custom board

2x TSE-PHY MICREL-Ethernet Ports A,B

 

A,B linked to PC NIC works fine (I send and transmit frames from PC to TSE and vice-versa) , I see 100 Mbps, Full Duplex, Auto MDI/MDI-X default enabled

 

Connecting TSE A to B with same crossed cable already tested before, PHYs never goes up!!!!

There is another manouvre to do to wakeup TSE-PHY???

 

Thanks to everyone knows this question!

 

Tags (1)
0 Kudos
14 Replies
SengKok_L_Intel
Moderator
115 Views

Hi, What is the Core variation of TSE that you selected? Do you perform any auto negotiation. Regards -SK
APaci1
Novice
115 Views

I'm using Quartus Prime 18.1. Autonegotiation is on on both TSE. Chip PHY is micrel KSZ9031MNX. I'm trying at 100 Mbps.

I'm using a simple sw confioguration from Eclipse, written to read/write PHY registrer using MDIO interface on TSE, without problem. I can read/write all my PHY registers

 

  • With PC NIc Card : Link goes UP 100 Mb full-duiplex (cross cable, but runs with straight one due to MDI-X capabiliy)
  • Connecting TSE A to B with same cross cable Link never goes UP

 

So, circuits and HW should be ok, PC NIC connection is stable... When connect TSE togheters, probably there is some actions at low network level that NIC PC card does and both TSE+PHY don't performs. I must discover what..... :-(

(I tried to connect TSE_A to TSE_A on MII internal side, inside FPGA and they runs fine with my frames applications.)

If anyone knows this issue, I say thanks for any suggestion

SengKok_L_Intel
Moderator
115 Views

​Hi

 

Based on my understanding, the FPGA only consist of MAC, where the PCS and PHY are external CHIP. The auto negotiation is occurring at the PCS level, I would suggest you to disable the auto negotiation, and fix the data rate at 100 Mb and see if it make any difference.

 

 

Regards -SK   

APaci1
Novice
115 Views

Nothiong to do.. if I fix speed both PHY doensnt' go UP and it is impossible to sending any thing.

I tested them connecting to a D-link commercial 1Gb switch, limiting test to 100 mbps. They go up immediatly and I can sent/receive frames , no problem.

 

Only when i connect one each other, PHY cannot go up. But should be possible connect 2 PHY each other, I think!!

 

 

Another question... TSE MAC FILTERING seems don't run.. I set on TSE main control register TSE_PROMIS_EN=0 and TSE_CTRL_FRM_ENA=1 .. so TSE must receive only frames directed to it (MacD = Mac TSE) but it remains to receive any frame on user side.... !!!!!!

 

If anyone has suggestions they are well accepted!!

 

Thanks

 

Filippo

SengKok_L_Intel
Moderator
115 Views

​Hi,

 

If this is using external PHY (consist PCS and PMA), and the FPGA is only consist MAC, then I would suggest you to double check with the external PHY datasheet, and see if there is any setting required. I suspect the auto-negotiation is not success, and this is why i suggest to disable it, and see if it works.

 

If you set PROMIS_EN = 0, and yes, it should filtering if the destination address does not match. What is the resisters mac_0 ,mac_1, and supplementary address that you configure? And what address that you receive but not filter? Did you try to do a software reset (SW_RESET)?

 

Regards -SK

APaci1
Novice
115 Views

Hello! Sorry for my delay, but we have a bunch of damned word to find 1000 mbps issue on PHY Microchip. Problem was hardware: some surge protecions on line side make 1000mbps connection impossible. After dismantle these components now both Ethernet connections on my custom board runs at 1000 mbps (!)

 

Now I'm fighting with TSE_MAC filtering problem. I set PROMISE_EN=0 and TSE_CRTL_FRM_ENA=1,

I set primary TSE Mac only. When it runs, on "user side" I see that Frames arrives with any Mac D , tse should filters only MAcD=Mac TSE .... I believe... but filter doesn't run. :-(((

 

Tomorrow I'll check better!!! Probably I fails or omits another setting on TSE to activate this filter

SengKok_L_Intel
Moderator
115 Views

Thanks you for the update. Yes, please double check. The TSE address filter should work.
APaci1
Novice
115 Views

Nothing!! I checked my TSE configuration, Promise_en=0, TSE_CRTL_FRM_ENA=1 but any frame reach user RX side.. I programmed a TSE_MAC address with a dummy one , as per 0xFFEEDDBBCCAA but any frames passes.

My HW settings are:

 

Quartus 18.1 std version

GMII/MII only (Arria10)

10/100/1000 Ethernet Mac

8 bit interface

Fifos enabled, 4096 bytes

Mac 10/100 fdpx, local loopback, include stat counters, enable flow control ENABLED

Mac Primary programmed

 

And for SW settings

// TSE_MAC Command Config Register

 

#define TSE_ENA_TX               1   // 0 Only these first 2 bit are resets from soft TSE reset command!

#define TSE_ENA_RX               1   //

#define TSE_XON_GEN            0   //   1->Command to transmit XON PAUSE FRAME to remote device

#define TSE_ETH_SPEED        1    //   10/100Mbps = 0 1000Mbps = 1

 

#define TSE_PROMIS_EN        0    //   Must be = 0 to enable MAC Address filtering!

#define TSE_PAD_EN               1   //   Padding enabled for shortest frames

#define TSE_CRC_FWD            0    //   1 = FWD CRC, 0 = removes CRC from frame (PC NICS usually removes CRC) Remove is intended to user-side application, on received eth frames.

#define TSE_PAUSE_FWD       0

//-------------------------------------------------------------------------------------------------------------

#define TSE_PAUSE_IGNORE        0  // 8 If 1, Device doesn't make PAUSE on control flow transmissions                                   

#define TSE_TX_ADDR_INS          0   //   1 to overwrite TSE programmed MAC as Source Mac on tx frames!

#define TSE_HD_ENA                0  //   Half duplex enable

#define TSE_EXCESS_COL            0  //   R.O. --> if 1 , frame discarded after 16 collisions detected

 

#define TSE_LATE_COL             0   //   R.O. --> late collisions detected

#define TSE_SW_RESET             0

#define TSE_MHASH_SEL            0

#define TSE_LOOP_ENA             0    // 15 1=LOOP TEST ENABLED (on GMII/MII SIDE, frames from PHY are resend to it)

//-------------------------------------------------------------------------------------------------------------

#define TSE_TX_ADDR_SEL         0x0 // bit16,17,18 = 000 Source MAC address selection 3 bits 000=primary address om Mac_0/Mac_1 regs

#define TSE_MAGIC_ENA            0  // 19

#define TSE_SLEEP                0  // 20

#define TSE_WAKEUP                0  // 21 1->Command to transmit XOFF PAUSE FRAME to remote device

#define TSE_XOFF_GEN               0  // 22 1->Command to transmit PAUSE FRAME to remote device

#define TSE_CTRL_FRM_ENA      1  // 23 FILTER RX FRAMES : ONLY MAC ADDRESSED PASS (!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!)

#define TSE_NO_LGTH_CHECK         0  // 24 1-> omits Payload=LenType check ; 0-> perform control

#define TSE_ENA_10                0   // 25 0 -->100Mbps    1 --> 10Mbps

//-------------------------------------------------------------------------------------------------------------

#define TSE_RX_ERR_DISC          0  // 26 1-> DISCARDS ERRONEUS FRAMES !

#define TSE_DISABLE_RD_TIMEOUT      0  // 27

//                                         28,29,30 RESERVED

#define TSE_CNT_RESET             0  // 31

 

 

 

 

 

 

SengKok_L_Intel
Moderator
115 Views

It seem like this is your primary mac address 0xFFEEDDBBCCAA. ​Did you enable the supplemental MAC unicast address? If yes, please configure the supplemental MAC address same as primary address for testing purpose. Could you please provide a signal tap or waveform on the Receiver Avalon ST interface & GMII interface to confirm the MAC address you received is expected but does not get filter out.

 

   

APaci1
Novice
115 Views

Ok, primary test addr is as you read.

I traced my Avalon ST interface and I receive all the Frames with any Destination Macs, as per attached files.

I don't use supplementary macs. Now I try to write all suppl. macs 0,1,2,3 with same primary address (FFEEDDBBCCAA) but I readback 0x0!! Instead, primary MAc is written and read correctly

APaci1
Novice
115 Views

this is capture on avalon side, any frame with MAcD different from Primary MAC enter anyway... :-()

SengKok_L_Intel
Moderator
115 Views

For unicast address, bit 0 of the destination address is 0, but for your case the bit 0 is 1 (F). Could you please try the address below?

 

mac_0 = 0xccddeeff

mac_1 = 0x0000aabb

 

Or

 

mac_0 = 0x42E90700

mac_1 = 0x000028AC

 

 

APaci1
Novice
115 Views

Thnaks, I try set TSE_MAC Addr 0/1 and all secondary Macs to mac having 0 on lsbit as you suggest, but on avalon side results is the same, I receive all macs that arrives on this network segment... :-(

SengKok_L_Intel
Moderator
115 Views

​I have run the simulation and confirm the address filtering is working fine from my site.

 

Could you please try the following setting, and read back the register to confirm?

 

  1. Address 2 command_config = 0x048002b
  2. Address 3 MAC_0 = 0x22334450
  3. Address 4 MAC_1= 0x 0000EE11

 

Could you please also refer to the link below, section 5.3.1 and follow the recommended initialization sequences?

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf

 

 

 

 

 

 

Reply