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Hi community,
I have a DE10-Nano board where I would like to prototype my own 100 Mbit MAC design instead of the one (EMAC0 or EMAC1) hardwired in the HPS. From what I understand, the MII interface of the on-board PHY is connected to pins which are mapped to the HPS I/O. So how can I route these MII signals directly to the FPGA fabric (without using the HPS EMAC)? I saw in the Platform Design interface that one is allowed to multiplex these pins via 'loan I/Os" or "GPIOs", but I am not sure of which method is correct. thanks for your help:o:o MarcoLink Copied
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