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Honored Contributor I
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Controlling LCD through NIOS

I am working with the Altera DE-2 kit, Cyclone II: EP2C35F672C6 FPGA. 

 

If I use VHDL I am able to use the LCD on the board but attempting top do so in NIOS is not working. I tried to use the binary count example, which works for the HEX and LED display but not LCD.  

 

My SOPC contains: 

8 MB - SDRAM 

8 bit - Switch PIO 

8 bit - LED PIO 

LCD Display  

JTAG Interface 

System ID 

 

VHDL Code: 

 

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY lights IS PORT(SW: IN STD_LOGIC_VECTOR(7 DOWNTO 0); KEY: IN STD_LOGIC_VECTOR(3 DOWNTO 0); CLOCK_50: IN STD_LOGIC; LEDG: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); HEX: OUT STD_LOGIC_VECTOR(15 DOWNTO 0); LCD_ON, -- Power ON/OFF LCD_BLON, -- Back Light ON/OFF LCD_RW, -- Read/Write Select, 0 = Write, 1 = Read LCD_EN, -- Enable LCD_RS : out std_logic; -- Command/Data Select, 0 = Command, 1 = Data LCD_DATA : inout std_logic_vector(7 downto 0); -- Data bus 8 bits DRAM_CLK, DRAM_CKE : OUT STD_LOGIC; DRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); DRAM_BA_0, DRAM_BA_1 : BUFFER STD_LOGIC; DRAM_CS_N, DRAM_CAS_N, DRAM_RAS_N, DRAM_WE_N : OUT STD_LOGIC; DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); DRAM_UDQM, DRAM_LDQM : BUFFER STD_LOGIC ); END lights; ARCHITECTURE Structure OF lights IS COMPONENT nios_system port ( -- 1) global signals: signal clk_0 : IN STD_LOGIC; signal reset_n : IN STD_LOGIC; -- the_button_pio signal in_port_to_the_button_pio : IN STD_LOGIC_VECTOR (7 DOWNTO 0); -- the_lcd_display signal LCD_E_from_the_lcd_display : OUT STD_LOGIC; signal LCD_RS_from_the_lcd_display : OUT STD_LOGIC; signal LCD_RW_from_the_lcd_display : OUT STD_LOGIC; signal LCD_data_to_and_from_the_lcd_display : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- the_led_pio signal out_port_from_the_led_pio : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- the_sdram_0 signal zs_addr_from_the_sdram_0 : OUT STD_LOGIC_VECTOR (11 DOWNTO 0); signal zs_ba_from_the_sdram_0 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); signal zs_cas_n_from_the_sdram_0 : OUT STD_LOGIC; signal zs_cke_from_the_sdram_0 : OUT STD_LOGIC; signal zs_cs_n_from_the_sdram_0 : OUT STD_LOGIC; signal zs_dq_to_and_from_the_sdram_0 : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0); signal zs_dqm_from_the_sdram_0 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); signal zs_ras_n_from_the_sdram_0 : OUT STD_LOGIC; signal zs_we_n_from_the_sdram_0 : OUT STD_LOGIC; -- the_seven_seg_pio signal out_port_from_the_seven_seg_pio : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ); END COMPONENT; COMPONENT sdram_pll PORT(inclk0: IN STD_LOGIC; c0: OUT STD_LOGIC; c1: OUT STD_LOGIC); END COMPONENT; SIGNAL DQM : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL BA : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL pll_cl: STD_LOGIC; BEGIN DRAM_BA_0 <= BA(0); DRAM_BA_1 <= BA(1); DRAM_UDQM <= DQM(1); DRAM_LDQM <= DQM(0); --LCD_ON <= '1'; NiosII: nios_system PORT MAP (pll_cl, KEY(0), SW , LCD_EN,LCD_RS, LCD_RW,LCD_DATA, LEDG, DRAM_ADDR, BA, DRAM_CAS_N, DRAM_CKE, DRAM_CS_N, DRAM_DQ, DQM, DRAM_RAS_N, DRAM_WE_N, HEX); neg_3ns: sdram_pll PORT MAP(CLOCK_50, DRAM_CLK, pll_cl); END Structure;
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2 Replies
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Honored Contributor I
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I finally got this to work, started quartus project from scratch with the previously mentioned components, the code above except I added: 

 

LCD_ON <= '1'; 

LCD_BLON <= '1'; 

 

The one thing that is very frustrating is why the NIOS IDE keeps throwing an elf error or system id mismatch error for what seems to be no apparent reason. 

 

For example, I add a component in the SOPC, or an input in the entity block, update the BSP and suddenly I will see an error message that the elf can't be downloaded or the the system ID does not match the ID value on the board. No major changes in the quartus project, non at all on the NIOS C code, and for some reason error.
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Highlighted
Honored Contributor I
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Hi All 

I've the same issue... every times I usually clear all configuration and I create a new one...
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